M306V2EEFS datasheet(175/271 Pages) RENESAS

175 / 271 page

Rev.1.40

Oct 06, 2004 page 175 of 269

M306V2ME-XXXFP, M306V2EEFP

2.14.12 Interrupt Request Generating Circuit

The interrupt requests as shown in Table 2.14.3 are generated by combination of the following bits; bits 6

and 7 of the caption position register (address 026616). Read out the contents of data registers 1, 2 and

the contents of bits 3 to 7 of the clock run-in detect register after the occurrence of a data slicer interrupt

request.

Slice Line Specification Mode

CPS

Completion Flag 1

(bit 0 of DSC2)

Completion Flag 2

(bit 5 of CPS)

Caption Data

Line 21

A line specified by

bits 4 to 0 of CPS

Line 21

A line specified by

bits 4 to 0 of CPS

Invalid

A line specified by

bits 4 to 0 of CPS

16-bit data of line 21

16-bit data of a line specified

by bits 4 to 0 of CPS

16-bit data of line 21

16-bit data of a line specified

by bits 4 to 0 of CPS

Invalid

16-bit data of a line specified

by bits 4 to 0 of CPS

ContentsofCaptionDataLatchCompletionFlag

Contents of 16-bit Shift Register

bit 7

bit 6

CPS: Caption position register

DSC2: Data slicer control register 2

Table 2.14.2 Contents of caption data latch completion flag and 16-bit shift register

CPS

Occurrence Sources of Interrupt Request at End of Data Slice Line

After slicing line 21

After a line specified by bits 4 to 0 of CPS

After slicing line 21

Table 2.14.3 Occurrence sources of Interrupt request

CPS: Caption position register

Figure 2.14.12 Data slicer reserved register i (i = 1, 2)

Data slicer reserved register i (i =1, 2)

Symbol

Address

When reset

DR1

026816

0016

DR2

026716

0016

Reserved bits

Bit symbol

Bit name

Description

Mest always be set to “0”

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