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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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M306V2EEFS датащи(PDF) 167 Page - Renesas Technology Corp |
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M306V2EEFS датащи(HTML) 167 Page - Renesas Technology Corp |
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167 / 271 page  Rev.1.40 Oct 06, 2004 page 167 of 269 M306V2ME-XXXFP, M306V2EEFP Figure 2.14.2 Termination of data slicer input/output pins when data slicer circuit and timing generating circuit is in OFF state Figure 2.14.3 Termination of data slicer input/output pins when timing signal generating circuit is in ON state <When data slicer circuit and timing signal generating circuit is in OFF state> <When using a reference clock generated in timing signal generating circuit as OSD clock> AVCC HLF VHOLD CVIN Apply the same voltage as VCC to AVCC pin. Open Open Leave HLF pin open. Leave VHOLD pin open. Pull-up CVIN pin to Vcc through a resistor of 5 k Ω or more. 5 k Ω or more 99 2 1 100 Apply the same voltage as VCC to AVCC pin. Connect the same external circuit as when using data slicer to HLF pin. Leave VHOLD pin open. Pull-up CVIN to VCC through a resistor of 5 k Ω or more. AVCC VHOLD CVIN Open 5 k Ω or more HLF 1 k Ω 200pF 1 µF 99 2 1 100 2.14.1 Notes when not Using Data Slicer When bit 0 of data slicer control register 1 (address 026016) is “0,” terminate the pins as shown in Figure 2.14.2 When both bits 0 and 2 of data slicer control register 1 (address 026016) are “1,” terminate the pins as shown in Figure 2.14.3. |
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