M306V2EEFS datasheet(147/271 Pages) RENESAS

147 / 271 page

Rev.1.40

Oct 06, 2004 page 147 of 269

M306V2ME-XXXFP, M306V2EEFP

(13) Precautions when using multi-master I2C-BUS interface i

s BCLK operation mode

Select the no-division mode and set the main clock frequency to f(XIN) = 10 MHz.

s Used instructions

Specify byte (.B) as data size to access multi-master I2C-BUS interface i-related registers.

s Read-modify-write instruction

The precautions when the read-modify-write instruction such as BSET, BCLR etc. is executed for

each register of the multi-master I2C-BUS interface are described below.

•I2Ci data shift register (IICiS0)

When executing the read-modify-write instruction for this register during transfer, data may

become a value not intended.

•I2Ci address register (IICiS0D)

When the read-modify-write instruction is executed for this register at detecting the STOP con-

______

dition, data may become a value not intended. It is because hardware changes the read/write

bit (RBW) at the above timing.

•I2Ci status register (IICiS1)

Do not execute the read-modify-write instruction for this register because all bits of this register

are changed by hardware.

•I2Ci control register (IICiS1D)

When the read-modify-write instruction is executed for this register at detecting the START

condition or at completing the byte transfer, data may become a value not intended. Because

hardware changes the bit counter (BC0–BC2) at the above timing.

•I2Ci clock control register (IICiS2)

The read-modify-write instruction can be executed for this register.

•I2Ci port selection register (IICiS2D)

Since the read value of high-order 4 bits is indeterminate, the read-modify-write instruction

cannot be used.

•I2Ci transmit buffer register (IICiS0S)

Since the value of all bits is indeterminate, the read-modify-write instruction cannot be used.

Fig. 2.11.45 Address data communication format

SSlave address

DataA

DataA/A

R/W

7 bits“0”1 to 8 bits

1 to 8 bits

SSlave address

Data

AData

7 bits

“1”

1 to 8 bits

(1) A master-transmitter transmits data to a slave-receiver

Slave address

1st 7 bits

Data

7 bits“0”8 bits1 to 8 bits

(2) A master-receiver receives data from a slave-transmitter

Slave address

2nd byte

Data

A/A

1 to 8 bits

Slave address

1st 7 bits

7 bits“0”8 bits7 bits

(3) A master-transmitter transmits data to a slave-receiver with a 10-bit address

Slave address

2nd byte

Data

1 to 8 bits

Slave address

1st 7 bits

Data

1 to 8 bits

“1”

(4) A master-receiver receives data from a slave-transmitter with a 10-bit address

S : START condition

P : STOP condition

A : ACK bit

R/W : Read/Write bit

Sr :Restart condition

From master to slave

From slave to master

R/W

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