ORSPI4 datasheet(143/263 Pages) LATTICE

143 / 263 page

Lattice Semiconductor

ORCA ORSPI4 Data Sheet

143

FIFOs (Figure 71).

• MC_RCLK from the FPGA, which controls the FPGA-side accesses to the Read Instruction and Read Data

FIFOs.

• The main clock for the unit is selected by MC_ICK_SEL (conﬁguration register 30B03[2:3]) which controls all

remaining clocking, including the clocks supplied to the external QDR-II SRAM. This clock can be sourced as fol-

lows:

– MC_ICK_SEL = 0 selects the dedicated Memory Controller external clock input MCREFCLK = Freq_In

– MC_ICK_SEL = 1 selects the SPIA unit's external clock ATREFCLK = Freq_In;

– MC_ICK_SEL = 2 selects the SPIB unit's external clock BTREFCLK = Freq_In, or

– MC_ICK_SEL = 3 selects the FPGA-supplied signal F_MC_REFCLK= Freq_In.

The above-selected clock, can then be modiﬁed in frequency, by MC_OCK_SEL (conﬁguration register

30B03[7]) as follows:

– MC_OCK_SEL = 0 selects a PLL, such that Freq_Out = (Freq_In * (PLL_N + 1)/(2 * (PLL_M + 1))); or

– MC_OCK_SEL = 1 selects a divide-by-2, such that Freq_Out = (Freq_In / 2).

The PLL_N value is obtained from the conﬁguration register 30B04[1:3]. PLL_M value is obtained from conﬁgu-

ration register 30B04[5:7].

At the right side of the four internal FIFOs in Figure 71, the data is transferred as two 36-bit words per Freq_Out

clock cycle, but is then time-multiplexed into a single 36-bit DDR bus operating at frequency (Freq_Out * 2) for

transfer to the external QDR-II SRAM. The clock supplied to the QDR-II SRAM is at frequency Freq_Out.

Figure 79 through Figure 85 show the timing diagrams for the embedded controller/FPGA interface.

Figure 79. Data: F_MC_WD[73:0], F_MC_WI[31:0], F_MC_RI[31:0]

Clock: F_MC_WCLK

3.5/0.5 ns

1.5/0.5 ns

FIFO

Delay

2.4/ 0.75 ns

FPGA

Embedded Core

1.1/ 0.74 ns

Setup= 1.6 ns

Hold = 0.3 ns

NOTE: Delays represent average max/min values, not absolute values

Delay

Actual delay values are used by

ispLEVER

Clock Buffer Delay

Relative to Data

ORSPI4 датащи(PDF) 143 Page - Lattice Semiconductor