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ORSPI4 датащи(PDF) 127 Page - Lattice Semiconductor

номер детали ORSPI4
подробное описание детали  Dual SPI4 Interface and High-Speed SERDES FPSC
PDF  263 Pages
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производитель  LATTICE [Lattice Semiconductor]
домашняя страница  http://www.latticesemi.com
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ORSPI4 датащи(HTML) 127 Page - Lattice Semiconductor

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Lattice Semiconductor
ORCA ORSPI4 Data Sheet
127
For receive quad alignment, RSYS_CLK_1 and RSYS_CLK_2 can be tied together as shown in Figure 66.
Figure 66. Clocking for a Quad Receive Clocking for a Dual Alignment in a Single Quad
Multi-channel Alignment Configuration
Register settings for multi-channel alignment are shown in Table 36.
Table 36. Multi-Channel Alignment Modes
To align all 4 channels:
• FMPU_SYNMODE_[A:D] = 01
• FMPU_SYNMODE_B[A:D] = 11
To align two channels:
• FMPU_SYNMODE_[A:B] = 10 for channel A and B
• FMPU_SYNMODE_[C:D] = 10 for channel C and D
To enable/disable synchronization signal of individual channel within a multi-channel alignment group:
• FMPU_STR_EN_x = “1” enabled
• FMPU_STR_EN_x = “0” disabled where x is one of [A:D].
To resynchronize a multi-channel alignment group set the following bit to zero, and then set it to one:
• FMPU_RESYNC4 for quad [A:D]
• FMPU_RESYNC2_1 for twin channel [A:B]
Register Bits
FMPU_SYNCMODE_xx[0:1]
Mode
00
No multi-channel alignment
10
Twin channel alignment
01
Quad channel alignment
Common Logic
Channel A
Channel B
Channel D
Channel C
REFCLK[P:N]
2
156.25 MHz
RCK78
RWCKA
RWCKC
RSYS_CLK_1
RSYS_CLK_2
FPGA
Logic
Four Bidirectional Channels
of 3.125 Gbits/s
Serial Data
RWCKB
RWCKD
All Clocks at
78.125 MHZ
TCK78
TSYS_CLK_A
TSYS_CLK_B
TSYS_CLK_C
TSYS_CLK_D



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