PM6681ATR datasheet(39/47 Pages) STMICROELECTRONICS

39 / 47 page

PM6681A

Design guidelines

39/47

Typical components values are: R = 47

Ω and C = 1 µF.

●

VREF capacitor. A 10 nF to 100 nF ceramic capacitor on VREF pin must be added to

ensure noise rejection.

●

LDO5 output capacitors. Bypass the output of each linear regulator with 1

µF ceramic

capacitor closer to the LDO pin and a 4.7

µF tantalum capacitor (ESR = 2 Ω). In most

applicative conditions a 4.7

µF ceramic output capacitor can be enough to ensure

stability.

●

Bootstrap circuit. The external bootstrap circuit is represented in the next figure:

Figure 43.

Bootstrap circuit

The bootstrap circuit capacitor value CBOOT must provide the total gate charge to the high

side MOSFET during turn on phase. A typical value is 100 nF.

The bootstrap diode D must charge the capacitor during the off time phases. The maximum

rated voltage must be higher than VINmax.

A resistor RBOOT on the BOOT pin could be added in order to reduce noise when the phase

node rises up, working like a gate resistor for the turn on phase of the high side MOSFET.

9.8

Design example

The following design example considers an input voltage from 7 V to 16 V. The two switching

outputs are OUT1 = 1.5 V and OUT2 = 1.05 V and must deliver a maximum current of 5 A.

The selected switching frequencies are about 290 kHz for OUT1 section and about 425 kHz

for OUT2 section (see Table 1).

9.8.1

Inductor selection

OUT1: ILOAD = 2.5 A, 45 % ripple current.

We choose standard value L = 8.2

µH.

∆I

L(max) = 1.16 A @ VIN = 24 V.

ILRMS = 2.53 A

P H

O 5

B O

O O

O T

KHz

290

)

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