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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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PM6681ATR датащи(PDF) 37 Page - STMicroelectronics |
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PM6681ATR датащи(HTML) 37 Page - STMicroelectronics |
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37 / 47 page  PM6681A Design guidelines 37/47 where ∆I L is the inductor current ripple and VRIPPLE is the overall ripple of the T node voltage. It should be chosen higher than approximately 30 mV. The new closed loop gain depends on CINT. In order to ensure stability it must be verified that: Equation 30 Where: Equation 31 where RTOT is the sum of the ESR of the output capacitor Rout and the equivalent ESR given by the virtual ESR network RESR. Moreover CINT must meet the following condition: Equation 32 Where k is a free design parameter greater than 3 and determines the minimum integrator capacitor value CINT: Equation 33 C must be selected as shown: Equation 34 R must be chosen in order to have enough ripple voltage on integrator input: Equation 35 R1 can be selected as follows: OUT Z m INT V Vr f 2 g C × × π > TOT out Z R C 2 1 f × × π = TOT out Z sw R C 2 k f k f × × π = × > OUT Z sw m INT V Vr f k f 2 g C × ⎟ ⎠ ⎞ ⎜ ⎝ ⎛ − × π > INT C 5 C × > C R L R ESR × = |
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