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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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PM6681ATR датащи(PDF) 36 Page - STMicroelectronics |
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PM6681ATR датащи(HTML) 36 Page - STMicroelectronics |
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36 / 47 page  Design guidelines PM6681A 36/47 Equation 27 Due to the capacitive divider (CINT, Cfilt), the ripple voltage at the COMP pin is given by: Equation 28 Where VRIPPLEout is the output ripple and q is the attenuation factor of the output ripple. If the ripple is very small (lower than approximately 30 mV), a further compensation network, named virtual ESR network, is needed. This additional part generates a triangular ripple that is added to the ESR output voltage ripple at the input of the integrator network. The complete control schematic is represented in Figure 40. Figure 40. Virtual ESR network The T node voltage is the sum of the output voltage and the triangular waveform generated by the virtual ESR network. In fact the virtual ESR network behaves like a further equivalent ESR RESR. A good trade-off is to design the network in order to achieve an RESR given by: Equation 29 filt INT filt INT CUT INT C C C C f 2 1 R + × × × π = q V C C C V V RIPPLEout filt INT INT RIPPLEout RIPPLEINT × = + × = out L RIPPLE ESR R I V R − ∆ = |
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