ST92163 datasheet(142/224 Pages) STMICROELECTRONICS

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ST92163 - USB PERIPHERAL (USB)

USB INTERFACE (Cont’d)

CTR INTERRUPT FLAGS (CTRINF)

R253 - Read/Write

Reset Value: 00xx xxx0 (xxh)

Note: This register is used only when the SDNAV

bit is 1.

Bit 7:6 = Reserved. These bits are fixed by hard-

ware at 0.

Bit 5 = INTO:

Interrupt occurred.

Set by hardware when SDNAV = 1 in the same

way as the CTRO bit in USBIVR register is set

when SDNAV = 0.

Bit 4:1 = ENID[3:0]:

Endpoint identifier.

Set by hardware when SDNAV = 1 in the same

way as V[3:0] bits in USBIVR register are set when

SDNAV = 0.

Bit 0 = Reserved. This bit is fixed by hardware at 0.

FRAME NUMBER REGISTER HIGH (FNRH)

R254 - Read-only

Reset Value: 0000 0xxx (0xh)

Bit 7 = RXDP.

Set/cleared by hardware to indicate D+ upstream

port data line status.

Bit 6 = RXDM.

Set/cleared by hardware to indicate D- upstream

port data line status.

Bit 5 = LCK:

Locked.

Set by hardware when at least two consecutive

SOF packets have been received after the end of

a USB reset condition or after the end of a USB

resume sequence.

0: Frame timer not locked

1: Frame timer locked

Note: Once locked, the frame timer remains in this

state until a USB reset or USB suspend event oc-

curs.

Bits 4:3 = LSOF[1:0]:

Lost SOF.

Set by hardware when an ESOF interrupt is gener-

ated, counting the number of consecutive SOF

packets lost. On reception of a SOF packet, these

bits are cleared.

Bits 2:0 = FN[10:8]:

Frame Number bits 10:8.

These bits contain the most significant bits of the

Frame number received with the last received

SOF packet. These bits are updated when a SOF

interrupt is generated.

FRAME NUMBER REGISTER LOW (FNRL)

R255 - Read-only

Reset Value: xxxx xxxx (xxh)

Bits 7:0 = FN[7:0]:

Frame Number bits 7:0.

Set by hardware, this register contains the least

significant bits of the 11-bit frame number con-

tained in the last received SOF packet. The 3 re-

maining most significant bits are stored in the

FNRH register. This register is updated when a

SOF interrupt is generated.

8.3.4.2 Device and Endpoint specific Registers

For each function a DADDR register is available to

store the device address and for each endpoint a

pair of EPnR registers is available to store end-

point specific information.

INTO

ENID3 ENID2 ENID1 ENID0

RXDP RXDM

LCK

LSOF1 LSOF0 FN10

FN9

FN8

FN7

FN6

FN5

FN4

FN3

FN2

FN1

FN0

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