ST92163 datasheet(138/224 Pages) STMICROELECTRONICS

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ST92163 - USB PERIPHERAL (USB)

USB INTERFACE (Cont’d)

8.3.4 Register Description

USB registers can be divided into three groups:

– Common registers (page 15): interrupt registers

and USB control registers.

– Function and endpoint registers (pages 15, 4

and 5 depending on how many endpoints are im-

plemented): USB function addresses and end-

point status/configurations.

– Extra registers (page 60): device configuration.

8.3.4.1 Common registers

These registers affect all endpoints in the USB in-

terface. They are all mapped in the same ST9 reg-

ister page (page number 15).

The USB interface implements vectorized inter-

rupts: through a vector table it is possible to auto-

matically identify the starting address of each In-

terrupt Service Routine. The vector table contains

the 16-bit addresses pointing to each of the inter-

rupt service routines related to the CTR interrupt

for each endpoint. Other two 8-bit locations are

used to store the address of the service routine

handling the interrupts described in the USBISTR

edged, the USBIVR register provides a vector

pointing to the location in the vector table, contain-

ing the start address of the interrupt service rou-

tine related to the serviced interrupt.

INTERRUPT VECTOR REGISTER (USBIVR)

R248 - Read/Write

Reset Value: xxxx xxx0 (xxh)

This register may be used in two different ways de-

pending on the value of the SDNAV bit in the

CTRL register.

– If SDNAV bit = 1, Bits 7:1 are user programmable

(bit 0 is fixed to 0). The software writes the ad-

dress of a vector pointing to a single interrupt

routine. The application program has to select

the routine related to the pending interrupts using

the USBISTR and CTRINF registers.

– If SDNAV = 0, this register is used as a vector

pointing to the 16-bit interrupt vectors in program

memory containing the start addresses of the in-

terrupt service routines related to the occurred

interrupt. If several interrupts are simultaneously

pending, hardware writes in this register the in-

terrupt routine address related to the highest pri-

ority pending interrupt.

In this case the meaning of each bit is:

Bits 7:6 = A[1:0]:

Vector table Address.

These two bits are user programmable and they

contain the two most significant bits of the interrupt

vector table. This allows the user to define the in-

terrupt vector table position inside the first 256 lo-

cations of program memory at 64 bytes boundary.

Bit 5 = CTRO:

Correct Transfer interrupt occurred.

0: CTR interrupt pending

1: One of the interrupt flags in the USBISTR regis-

ter is pending

Note: If several interrupts are simultaneously

pending, hardware writes this bit according to their

relative priorities as listed below starting from the

highest priority one to the lowest priority one:

– DMA Over/Underrun (see Table 24 and USBIS-

TR register description)

– Correct Transfer on isochronous endpoints (see

EPnRA register description)

– Correct Transfer on non-isochronous endpoints

(see EPnRA register description)

– Notification events (see Table 24 and USBISTR

Bits 4:1 = V[3:1]:

Endpoint Vector.

If CTRO = 1, these bits are written by hardware to

specify the endpoint identifier which has generat-

ed the CTR interrupt request.

If several CTR interrupts are pending, hardware

writes the endpoint identifier related to the end-

point with the highest priority. Endpoint priority is

defined according to the following rule: endpoint 0

has the highest priority, then endpoint 1 follows

and so on up to the highest endpoint register pair

(EP15) with the lowest priority.

If CTRO = 0, these bits are fixed to 1. In this case

only one interrupt vector is used for all the inter-

rupts defined in the USBISTR register.

CTRO

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