ST92163 datasheet(143/224 Pages) STMICROELECTRONICS

143 / 224 page

143/224

ST92163 - USB PERIPHERAL (USB)

USB INTERFACE (Cont’d)

DEVICE n ADDRESS (DADDRn)

R240 to R247 - Read/Write

Reset Value: 0000 0000 (00h)

Note: This register is also reset when a USB reset

is received from the USB bus or forced through bit

FRES in the USBCTLR register.

Bit 7 = EF:

Enable Function.

Set by software to enable the USB function whose

address is contained in the following ADD[6:0]

bits.

0: Function disabled

1: Function enabled

Bits 6:0 = ADD[6:0]:

Device Address.

Software must write into these bits the USB device

address assigned by the host PC during the enu-

meration.

ENDPOINT n REGISTER A (EPnRA)

(TRANSMISSION)

R240-R254 (even)

Read/Write

Reset value: 0000 0000 (00h)

These registers are used for controlling data trans-

mission. They are also reset when a USB reset is

received or forced through the FRES bit in the US-

BCTLR register.

Note: The CTR bits are not affected by a USB re-

set

Each endpoint has its EPnRA register where n is

the endpoint identifier in the range 0 to 15.

Bit 7 = CTR:

Correct Transfer.

Set by hardware when a transaction is successful-

ly completed on this endpoint; software can only

clear this bit.

0: No correct transfer occured

1: Correct transfer occured

Note: A transaction ended with a NAK or STALL

handshake does not set this bit, since no data is

actually transferred, as in the case of protocol er-

rors or data toggle mismatches. The CTR bit is

also used to perform flow control: while CTR=1, a

valid endpoint answers NAK to every transaction

addressed to it (except SETUP requests which are

simply ignored) until the application software ac-

knowledges the CTR event, resetting this bit. This

does not apply to isochronous endpoints where no

handshake phase is used.

Bit 6 = DTOG_TX:

Data Toggle, for transmission

transfers.

If the endpoint is non-isochronous, this bit contains

the

required

value

the data

toggle

bit

(0=DATA0, 1=DATA1) for the next data packet to

be transmitted. Hardware toggles this bit when the

ACK handshake is received from the USB host,

following a data packet transmission. If the end-

point is defined as a control one, hardware sets

this bit to 1 on reception of a SETUP PID ad-

dressed to this endpoint.

If the endpoint is isochronous, this bit is used to

support DMA buffer swapping since no data tog-

gling is used for this sort of endpoint and only

DATA0 packet are transmitted. Hardware toggles

this bit just after the end of data packet transmis-

sion, since no handshake is used for isochronous

transfers.

Note: this bit can be also written by software to in-

itialize it (mandatory when the endpoint is not a

control endpoint) or to force specific data toggle/

DMA buffer usage.

ADD6

ADD5

ADD4

ADD3

ADD2

ADD1

ADD0

CTR

DTOG_

STA T_

TX1

STAT_

TX0

PIDR1 PIDR0

CEP

ISO

ST92163 датащи(PDF) 143 Page - STMicroelectronics

ST92163 датащи(HTML) 143 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL