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ST92163 - INTERRUPTS

3.6 EXTERNAL INTERRUPTS

The standard ST9 core contains 8 external inter-

rupts sources grouped into four pairs.

INT7 is connected to 8 different I/O pins of Port 3.

Once these pins are programmed as alternate

function they are able to generate an interrupt.

Table 11. External Interrupt Channel Grouping

INT0 .. 6 have a trigger control bit TEA0,..TED1

(R242,EITR.0,..,7 Page 0) to select triggering on

the rising or falling edge of the external pin. If the

Trigger control bit is set to “1”, the corresponding

pending bit IPA0,..,IPD1 (R243, EIPR.0,..,6 Page

0) is set on the input pin rising edge, if it is cleared,

the pending bit is set on the falling edge of the in-

put pin. Each source can be individually masked

through

the

corresponding

control

bit

IMA0,..,IMD1 (EIMR.6,..,0). See Figure 27.

INT7 is falling edge sensitive only, bit EIMR.7 must

always be cleared.

The priority level of the external interrupt sources

can be programmed among the eight priority lev-

els with the control register EIPLR (R245). The pri-

ority level of each pair is software defined using

the bits PRL2, PRL1. For each pair, the even

channel (A0,B0,C0,D0) of the group has the even

priority level and the odd channel (A1,B1,C1,D1)

has the odd (lower) priority level.

Figure 26. Priority Level Examples

Figure 26 shows an example of priority levels.

Figure 27 gives an overview of the External inter-

rupt control bits and vectors.

– The source of the interrupt channel A0 can be

selected between the external pin INT0 (when

IA0S = “1”, the reset value) or the On-chip Timer/

Watchdog peripheral (when IA0S = “0”).

– The source of the interrupt channel A1 can be

selected between the external pin INT1 (when

AD-INT=“0”) or the on-chip ADC peripheral

(when AD-INT=“1”, the reset value).

– The source of the interrupt channel D0 can be

selected between the external pin INT6 (when

INT_SEL = “0”) or the on-chip RCCU.

Warning: When using channels shared by both

external interrupts and peripherals, special care

must be taken to configure their control registers

for both peripherals and interrupts.

Table 12. Multiplexed Interrupt Sources

External Interrupt

Channel

INT7

INT6

INTD1

INTD0

INT5

INT4

INTC1

INTC0

INT3

INT2

INTB1

INTB0

INT1

INT0

INTA1

INTA0

Channel

Internal Interrupt

Source

External Interrupt

Source

INTA0

Timer/Watchdog

INT0

INTA1

ADC

INT1

INTD0

RCCU

INT6

001

PL2 D PL1D PL2 C PL1 C PL2B PL1B PL2A PL1A

INT.D1:

INT.C1: 001=1

INT.D0:

SOURCE

PRIORITY

PRIORIT Y

SOURCE

INT.A0: 010=2

INT.A1: 011=3

INT.B1: 101=5

INT.B0: 100=4

INT.C0: 000=0

EIPLR

VR000151

100=4

101=5

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