| поискавой системы для электроныых деталей |
|
ST92163 датащи(PDF) 139 Page - STMicroelectronics |
|
|
|||||||||||||||||||||||||||||
ST92163 датащи(HTML) 139 Page - STMicroelectronics |
|
139 / 224 page ![]() 139/224 ST92163 - USB PERIPHERAL (USB) USB INTERFACE (Cont’d) Bit 0 = Reserved. This bit is fixed by hardware at 0. INTERRUPT STATUS REGISTER (USBISTR) R249 - Read/Write Register page: 15 Reset Value: 0000 0000 (00h) Each bit is set by hardware when the related event occurs. If one of these bits is set, the hardware clears the CTRO bit and sets the V[3:0] bits in the USBIVR register. In this way the USBIVR register will point to the interrupt vector containing the address of the service routine related to these interrupt sourc- es. If several bits are set only a single interrupt will be generated. Note: to avoid spurious clearing of some bits, it is recommended to clear them with a load instruction where all bits which must not be altered are set to 1, and all bits to be cleared are set to 0. Read- modify-write instructions like AND, XOR,... are to be avoided: consider the case of clearing bit 0 of USBISTR with an AND instruction, when only bit 7 of USBISTR is at 1 and the others at 0. First the microcontroller reads the content of USBISTR (=10h), then it clears bit 7 and writes the result (=00h) in USBISTR. If between the read and the write operations another bit were set by hardware (e.g. bit 5), writing 00h would clear it before the mi- croprocessor has the time to service the event. Table 24. Classification of Interrupt Sources: Bit 7 = Reserved. This bit is fixed by hardware at 0. Bit 6 = DOVR: DMA over/underrun. ST9 processor has not been able to answer a DMA request in time and the USB FIFO buffer is full or empty depending on the transfer direction (reception or transmission). The USB handles this event in the following way: during reception the ACK handshake packet is not sent, during transmission a bit-stuffing error is forced on the transmitted stream. In both cases the host will retry the transaction. The DOVR inter- rupt should never occur during normal operations. Bit 5 = ERR: Error. One of the errors listed below has occurred: – NANS: No answer. The timeout for a host re- sponse has expired. – CRC: CRC error. One of the received CRCs, ei- ther in the token or in the data, was wrong. – BST: Bit Stuffing error. A bit stuffing error was detected anywhere in the PID, data, and/or CRC. – FVIO: Framing format violation. A nonstandard frame was received (EOP not in the right place, wrong token sequence, etc.). – BUFOVR: Buffer overrun. A packet longer than the allocated DMA buffer has been received. 70 0 DOVR ERR ESUSP SUSP RESET SOF ESOF Interrupt Class DOVR DMA Over/Underrun event ERR Notification event ESUSP Notification event SUSP Notification event RESET Notification event SOF Notification event ESOF Notification event |
|
ссылки URL |
| Вашему бизинису помогли Аллдатащит? [ DONATE ] |
Что такое Аллдатащит | реклама | контакт | Конфиденциальность | Ссылка на техническое описание | обмен ссыками | поиск по производителю All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |