ST52F510 datasheet(21/106 Pages) STMICROELECTRONICS

21 / 106 page

ST52F510/F513/F514

21/106

3 ADDRESSING SPACES

ST52F510/F513/F514

has

six

separate

addressing spaces:

Program/Data Memory

Stacks

Input Registers

Output Registers

Configuration Registers

Each space is addressed by a load type instruction

that indicates the source and the destination space

in the mnemonic code (see Figure 3.1).

3.1 Memory Interface

The read/write operation in the space addresses

are managed by the Memory Interface, which can

recognize the type of memory addressed and set

the appropriate access time and mode.

In addition, the Memory Interface manages the In

Application Programming (IAP) functions in Flash

devices like writing cycle and memory write

protection.

Figure 3.1 Addressing Spaces

3.2 Register File

The Register File consists of 256 general purpose

8-bit RAM locations called “registers” in order to

recall the functionality.

The Register File exchanges data with all the other

addressing spaces and is used by the ALU to

perform all the arithmetic and logic instructions.

These instructions have any Register File address

as operands.

Data can be moved from one location to another by

using the LDRR instruction; see further ahead for

information on the instruction used to move data

between

the

File

and

the

other

addressing spaces.

3.3 Program/Data Memory

The Program/Data Memory consists of both non-

volatile memory (Flash, EEPROM) and RAM

memory benches.

Non-volatile memory (NVM) is mainly used to store

the user program and can also be used to store

permanent data (constant, look-up tables).

Each RAM bench consists of 256 locations used to

store run-time user data. At least one bench is

present in the devices. RAM benches are also

used to implement both System and User Stacks.

DPU

ALU

PERIPHERAL

BLOCK

INPUT REGISTERS

NON VOLATILE MEMORY

RAM BANKS

AND STACKS

PROGRAM/DATA MEMORY

STFive CORE

ON CHIP PERIPHERALS

OUTPUT

REGISTERS

CONFIGURATION

REGISTERS

PERIPHERAL

BLOCK

PERIPHERAL

BLOCK

LDER

LDRE

LDRI

LDCE

LDCR

DECISION

PROCESSOR

REGISTERS

LDFR

LDPE

LDPR

LDCNF

PROGRAM

COUNTER

PGSETR

GETPG

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