ST52F510 datasheet(94/106 Pages) STMICROELECTRONICS

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ST52F510/F513/F514

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Bit 7: EVF Event Flag

This bit is set by hardware as soon as an

event occurs. It is cleared by software

reading I2C_SR2 register in case of error

event or as described in Figure 14.3. It is also

cleared by hardware when the interface is

disabled (PE=0).

0: No event

1: One of the following events has occurred:

– BTF=1 (Byte received or transmitted)

– ADSL=1 (Address matched in Slave

mode while ACK=1)

– SB=1 (Start condition generated in Mas-

ter mode)

– AF=1 (No acknowledge received after

byte transmission)

– STOPF=1 (Stop condition detected in

Slave mode)

– ARLO=1 (Arbitration lost in Master

mode)

– BERR=1 (Bus error, misplaced Start or

Stop condition detected)

– Address byte successfully transmitted in

Master mode.

Bit 6: ADD10 10 bit addressing in Master Mode

This bit is set by hardware when the master

has sent the first byte in 10-bit address mode.

It is cleared by software reading I2C_SR2

cleared by hardware when the peripheral is

disabled (PE=0).

0: No ADD10 event occurred

1: The Master has sent the first address byte

Bit 5: TRA Transmitter/Receiver

When BTF is set, TRA=1 if a data byte has

been transmitted. It is cleared automatically

when BTF is cleared. It is also cleared by

hardware after detection of Stop condition

(STOPF=1), loss of bus arbitration (ARLO=1)

or when the interface is disabled (PE=0).

0: Data byte received (if BTF=1)

1: Data byte transmitted

Bit 4: BUSY Bus busy

This bit is set by hardware on detection of a

Start condition and cleared by hardware on

detection of a Stop condition. It indicates a

communication in progress on the bus. This

information is still updated when the interface

is disabled (PE=0).

0: No communication on the bus

1: Communication ongoing on the bus

Bit 3: BTF Byte transfer finished

This bit is set by hardware as soon as a byte

is correctly received or transmitted with

interrupt generation if ITE=1. It is cleared by

software reading I2C_SR1 register followed

by a read of I2C_IN or write of I2C_OUT

registers. It is also cleared by hardware when

the interface is disabled (PE=0).

– Following a byte transmission, this bit is

set after reception of the acknowledge

clock pulse. In case an address byte is

sent, this bit is set only after the EV6

event (see Figure 14.3). BTF is cleared

by reading I2C_SR1 register followed by

writing the next byte in I2C_OUT register.

– Following a byte reception, this bit is set

after transmission of the acknowledge

clock pulse if ACK=1. BTF is cleared by

reading I2C_SR1 register followed by

reading the byte from I2C_IN register.

The SCL line is held low while BTF=1.

0: Byte transfer not done

1: Byte transfer succeeded

Bit 2: ADSL Address matched (Slave Mode)

This bit is set by hardware as soon as the

slave address received matched with the

OAR register content or a general call is

recognized. An interrupt is generated if

ITE=1. It is cleared by software reading

I2C_SR1 register or by hardware when the

interface is disabled (PE=0).

The SCL line is held low while ADSL=1.

0: Address mismatched or not received

1: Received address matched

Bit 1: M/SL Master/Slave

This bit is set by hardware as soon as the

interface

Master

mode

(writing

START=1). It is cleared by hardware after

detecting a Stop condition on the bus or a

loss of arbitration (ARLO=1). It is also

cleared when the interface is disabled

(PE=0).

0: Slave mode

1: Master mode

Bit 0: SB Start bit (Master Mode)

This bit is set by hardware as soon as the

Start condition is generated (following a write

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