ST52F510 datasheet(88/106 Pages) STMICROELECTRONICS

88 / 106 page

ST52F510/F513/F514

88/106

Note: In 10-bit addressing mode, the comparison

includes the header sequence (11110xx0) and the

two most significant bits of the address.

Header matched (10-bit mode only): the interface

generates an acknowledgement pulse if the ACK

bit is set.

Address not matched: the interface ignores it and

waits for another Start condition.

Address matched: the interface generates in

sequence:

– Acknowledge pulse if the ACK bit is set.

– EVF and ADSL bits are set with an interrupt if the

ITE bit is set.

Afterwards, the interface waits for the I2C_SR1

Figure 14.3 Transfer sequencing EV1).

Next, in 7-bit mode read the I2C_IN register to

determine from the least significant bit (Data

Direction Bit) if the slave must enter Receiver or

Transmitter mode.

In 10-bit mode, after receiving the address

sequence the slave is always in receive mode. It

will enter transmit mode on receiving a repeated

Start condition followed by the header sequence

with matching address bits and the least significant

bit set (11110xx1).

Slave Receiver

Following reception of the address and after the

I2C_SR1 register has been read, the slave

receives bytes from the SDA line into the I2C_IN

byte, the interface generates the following in

sequence:

– Acknowledge pulse if the ACK bit is set

– EVF and BTF bits are set with an interrupt if the

ITE bit is set.

Afterwards, the interface waits for the I2C_SR1

14.3 Transfer sequencing EV2).

Slave Transmitter

Following the address reception and after the

I2C_SR1 register has been read, the slave sends

bytes from the I2C_OUT register to the SDA line

via the internal shift register.

The slave waits for a read of the I2C_SR1 register

followed by a write in the I2C_OUT register,

holding the SCL line low (see Figure 14.3

Transfer sequencing EV3).

When the acknowledge pulse is received:

– The EVF and BTF bits are set by hardware with

an interrupt if the ITE bit is set.

Closing slave communication

After the last data byte is transferred a Stop

Condition is generated by the master. The

interface detects this condition and sets:

– EVF and STOPF bits with an interrupt if the ITE

bit is set.

Afterwards, the interface waits for a read of the

I2C_SR2 register (see Figure 14.3 Transfer

sequencing EV4).

Error Cases

– BERR: Detection of a Stop or a Start condition

during a byte transfer. In this case, the EVF and

the BERR bits are set with an interrupt if the ITE

bit is set.

If it is a Stop then the interface discards the data,

released the lines and waits for another Start

condition.

If it is a Start then the interface discards the data

and waits for the next slave address on the bus.

– AF: Detection of a non-acknowledge bit. In this

case, the EVF and AF bits are set with an inter-

rupt if the ITE bit is set.

Note: In both cases, the SCL line is not held low;

however, SDA line can remain low due to possible

«0» bits transmitted last. At this point, both lines

must be released by software.

How to release the SDA / SCL lines

Set and subsequently clear the STOP bit while

BTF is set. The SDA/SCL lines are released after

the current byte is transferred.

14.4.2 Master Mode.

To switch from default Slave mode to Master mode

a Start condition generation is needed.

Start condition

Setting the START bit while the BUSY bit is

cleared causes the interface to switch to Master

mode (M/SL bit set) and generates a Start

condition.

Once the Start condition is sent:

– The EVF and SB bits are set by hardware with

an interrupt if the ITE bit is set.

Afterwards, the master waits for a read of the

I2C_SR1 register followed by a write in the

I2C_OUT register with the Slave address, holding

the SCL line low (see Figure 14.3 Transfer

sequencing EV5).

ST52F510 датащи(PDF) 88 Page - STMicroelectronics

ST52F510 датащи(HTML) 88 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL