ST52F510 datasheet(81/106 Pages) STMICROELECTRONICS

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ST52F510/F513/F514

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Recognition of a STOP condition transfers data

received

from

the

Recovery

Buffer

the

SCDR_RX buffer, adding the eventual ninth data

bit. After this operation, RXF flag (bit 5) of SCI

Status Input Register is set to logic level 1. The

Control Unit reads data from the SCDR_RX buffer

(in read-only mode) by reading the SCI_IN Input

instruction and provides a reset at logic level 0 to

the RXF flag.

If data of the Recovery Buffer is ready to be

transferred into the SCDR_RX buffer, but the

previous one has not been read by the Core, an

OVERRUN Error takes place: the SCI Status

condition. In this case, information that is stored in

the SCDR_RX buffer is not altered, but the one

that has caused the OVERRUN error can be

overwritten by new data deriving from the serial

data line.

13.1.1 Recovery Buffer Block .

This block is structured as a synchronized finite

state machine on the CLOCK_RX signal.

When the Recovery Buffer Block is in IDLE state it

waits for the reception of the correct 1 and 0

sequence representing START.

Recognition takes place by sampling the input RX

at CLOCK_RX frequency, which has a frequency

that is 16 times higher than CLOCK_TX. For this

reason, while the external transmitter sends a

single bit, the Recovery Buffer Block samples 16

states (from SAMPLE1 to SAMPLE16).

Analysis of the RX input signal is carried out by

checking three samples for each bit received.

If these three samples are not equal, then the

noise error flag, NSERR (bit 7), of SCI Status

be the one assumed by the majority of the

samples.

The procedure described above, allows SCI not to

becomes IDLE, because of a limited noise due to

an erroneous sampling, the transmission is

recognized as correct and the noise flag error is

set.

At the end of the cycle of the reception of a bit, the

Recovery Buffer Block will repeat the same steps 9

times: one step for each bit received, plus one for

the stop acquisition (10 times in case of 9-bit data,

double stop or parity check).

At the end of data reception the Recovery Buffer

Block will supply information about eventual frame

errors by setting the 1 FRERR flag (bit 6) of the SCI

Status Register to 1.

A frame error can occur if the parity check hasn’t

been successfully achieved or if the STOP bit has

not been detected.

the

Recovery

Buffer

Block

receives

consecutive bits at logic level 0, a Line Break

condition occurs and the related Interrupt Request

is sent.

13.1.2 SCDR_RX Block.

It is a finite state machine synchronized with the

clock master signal, CKM.

The SCDR_RX block waits for the signal of

complete reception from the Recovery Buffer in

order to load the word received. Moreover, the

SCDR_RX block loads the values of FRERR and

NSERR flag bits of the Status Register, and sets

the RXF flag to 1.

By using the LDRI instruction data is transferred to

that the SCDR_RX block is empty.

If new data arrives before the previous one has

been transferred to Register File, the overrun error

occurs and the OVERR flag of Status Register is

set to 1.

Figure 13.3 SCI Status Register

D7 D6 D5 D4 D3 D2 D1 D0

SCI_STATUS Input Register 37

TXEND - END TRANSMISSION

TXEM

- TRANSMISSION DATA REGISTER EMPTY

- RECEIVED NINTH BIT

NSERR - NOISE ERROR

NOT USED

OVERR - OVERRUN ERROR

RXF

- RECEIVE DATA REGISTER FULL

FRERR - FRAME ERROR

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