ST52F510 datasheet(66/106 Pages) STMICROELECTRONICS

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ST52F510/F513/F514

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external reference mode is chosen the Ain0

channel is not used and the first channel of the

conversion sequence becomes Ain1.

The converter uses a fully differential analog input

configuration for a better noise immunity and

precision performances.

Up to 8 multiplexed Analog Inputs are available. A

single signal or a group of signals can be

converted sequentially by simply programming the

starting address of the last analog channel to be

converted. Single or continuous conversion modes

are available.

The result of the conversion of each A/D channel is

stored in the 8-bit Input Register pairs (addresses

from 41 to 56 (029h-038h)) according to the 8-bit or

10-bit mode. The resolution of conversion (8 or 10

bit) can be chosen by programming the RESOL bit

of the AD_CR Configuration Register. In 8-bit

mode the eight most significative bits (9:2) of the

result of conversion is stored in the least

significative byte of the register pair and the most

significative is put to zero. In 10-bit mode the two

most significative bits (9:8) are stored in the most

significative byte of the register pair; the other bits

(7:0) are stored in the least significative byte.

In 10-bit mode the result of the conversion must be

read in two steps: the MSB and the LSB. The

peripheral has been designed to avoid the side

effects that can occur when the register are

modified between the reading of the two bytes. In

fact the latching of the input register pair is

disabled after the reading of the first byte and it is

enabled again after the reading of the second byte.

User should pay attention to complete the two

readings to guarantee the data of the conversion to

be latched.

When the converted signal is higher than VREF, an

overflow occurs. In this case the 8/10 bits result are

all set to 1 and the A/D Overflow Register bit

(address 39 027h) corresponding to the channel is

set to 1. The bit is reset at the next conversion

having no overflow occurrence.

ST52F510/F513/F514 Interrupt Unit provides one

maskable channel for the End of Conversion and

for the overflow control. It is possible to set the

interrupt source on EOC or on overflow or on both

by programming the INT0 and INT1 bits in the

AD_CR Configuration Registers.

Note: the A/D Converter interrupts are not enabled

unless the bit 0 (MSKAD) of the Configuration

A Power-Down programmable bit (POW) allows

the A/D converter to be set to a minimum

consumption idle status. A stabilization time is

required, after the Power On, before accurate

conversions can be performed.

10.2 Functional Description

The conversion is monotonic, meaning that the

result never decreases if the analog input doesn’t

and never increases if the analog input doesn’t.

If input voltage is less than Vss (voltage supply

low) then the result is equal to 00h.

The A/D converter is linear and the digital result of

the conversion is provided by the following

formula:

Where Reference Voltage is Vref - Vss.

The accuracy of the conversion is described in the

Electrical Characteristics Section of the device

datasheets.

The A/D converter is not affected by the WAIT

mode.

When the ICU enters HALT mode with the A/D

converter enabled, the converter is disabled until

HALT mode is exited and the start-up delay has

elapsed.

10.3 Operating Modes

Four main operating modes can be selected by

setting the values of the CONT and SEQ bit in the

A/D Configuration Register AD_CR.

10.3.1 One Channel Single Mode. In this mode

(CONT=0, SEQ=0), the A/D provides an EOC

signal after the end of the conversion of the

specified channel; then the A/D waits for a new

start event. The channel is identified by the bits

CH2-CH0 in the Configuration Register AD_CR,

while the bit STR is used to command the Start/

Stop.

10.3.2 Multiple Channels Single Mode. In

this

mode (CONT=0, SEQ=1) the A/D provides an

EOC signal after the end of the channels sequence

conversion

identified

the

three

AD_CR

Configuration Register bits CH2-0; then A/D waits

for a new start event.

10.3.3 One Channel Continuous Mode. In this

mode (CONT=1, SEQ=0) a continuous conversion

flow is entered by a start event on the selected

channel. At the end of each conversion, the

relative Input Register is updated with the last

conversion result, while the former value is lost.

The conversion continues until a stop command is

executed by writing a ‘0’ in the apposite AD_CR

Configuration Register bit STR.

Digitalresult

255

InputVoltage

ReferenceVoltage

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