ST52F510 datasheet(101/106 Pages) STMICROELECTRONICS

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ST52F510/F513/F514

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Figure 15.5 Clearing the WCOL bit (Write Collision Flag) Software Sequence

15.4.6 Overrun Condition.

An overrun condition occurs when the master

device has sent several data bytes and the slave

device hasn’t cleared the SPIF bit issued from the

previous data byte transmitted.

In this case, the receiver buffer contains the byte

sent after the SPIF bit was last cleared. A read to

the SPI_IN register returns this byte. All other

bytes are lost.

This condition is not detected by the SPI

peripheral.

15.4.7 Single Master and Multimaster Configu-

rations.

There are two types of SPI systems:

– Single Master System

– Multimaster System

Single Master System

A typical single master system may be configured,

using an ICU as the master and four ICUs as

slaves (see Figure 15.6).

The master device selects the individual slave

devices by using four pins of a parallel port to

control the four SS pins of the slave devices.

The SS pins are pulled high during reset since the

master device ports will be forced to be inputs at

that time, thus disabling the slave devices.

Note: In order to prevent a bus conflict on the

MISO line the master allows only one active slave

device during a transmission.

For more security, the slave device may respond to

the master with the data byte received. Then the

master will receive the previous byte back from the

slave device if all MISO and MOSI pins are

connected and the slave has not written its

SPI_OUT register.

Other transmission security methods can use ports

for handshake lines or data bytes with command

fields.

Multi-master System

A multi-master system may also be configured by

the user. Transfer of master control could be

implemented using a handshake method through

the I/O ports or by an exchange of code messages

through the serial peripheral interface system.

The multi-master system is principally handled by

the MSTR bit in the SPI_CR register and the

MODF bit in the SPI_STATUS_CR register.

Clearing sequence after SPIF = 1 (end of a data byte transfer)

1st Step

Read SPI_STATUS_CR

Read SPI_IN

Write SPI_IN

2nd Step

SPIF =0

WCOL=0

SPIF =0

WCOL=0 if no transfer has started

WCOL=1 if a transfer has started

Clearing sequence before SPIF = 1 (during a data byte transfer)

1st Step

2nd Step

WCOL=0

before the 2nd step

Read SPI_STATUS_CR

Read SPI_IN

Note: Writing in SPI_OUT regis-

ter instead of reading in SPI_IN

do not reset WCOL bit

Read SPI_STATUS_CR

THEN

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