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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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WM8580 датащи(PDF) 48 Page - Wolfson Microelectronics plc |
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WM8580 датащи(HTML) 48 Page - Wolfson Microelectronics plc |
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48 / 103 page  WM8580 Production Data w PD Rev 4.5 February 2008 48 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R8 CLKSEL 08h 5:4 TX_CLKSEL 01 S/PDIF Transmitter clock source 00 = ADCMCLK pin 01 = PLLACLK 10 = PLLBCLK 11 = MCLK pin Table 39 S/PDIF Transmitter Clock Control PRIMARY AUDIO INTERFACE RECEIVER (PAIF RX) The PAIF Receiver requires a left-right-clock (LRCLK) and a bit-clock (BCLK). These can be supplied externally (slave mode) or they can be generated internally by the WM8580 (master mode). Register R9, bit 5 selects master or slave mode. In Slave mode, the BCLK and LRCLK driving the PAIF Rx interface are the PAIFRX_BCLK and the PAIFRX_LRCLK pins. In master mode the BCLK and LRCLK driving the PAIF Rx are generated by the Master Mode Clock Gen module. The control of this module is described on page 22. The clock supplied to this module is selected by the PAIFRXMS_CLKSEL register bits. These bits select either MCLK, PLLACLK, or PLLBCLK Unless the S/PDIF Rx interface is enabled in which case the PAIF Rx clock is forced to use the MCLK pin since the PLLA and PLLB are not available in this mode. Figure 29 PAIF Rx Interface Clock Configuration REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R9 PAIF 1 09h 7:6 PAIFRXMS_ CLKSEL 00 PAIF Receiver Master Mode clock source 00 = MCLK pin 01 = PLLACLK 10 = PLLBCLK 11 = MCLK pin Table 40 PAIF Rx Master Mode Clock Control |
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