WM8580 datasheet(45/103 Pages) WOLFSON

45 / 103 page

Production Data

WM8580

PD Rev 4.5 February 2008

ADC INTERFACE

The ADC_CLKSEL register selects the ADC_CLK clock source from ADCMCLK, PLLACLK,

PLLBCLK, or MCLK.

If the S/PDIF receiver is enabled, PLLACLK and PLLBCLK are invalid for ADC operation, so the

choice is limited to ADCMCLK (default) or MCLK. Figure 27Error! Reference source not found.

illustrates this.

MCLK

ADCMCLK (MFP2)

PLLACLK

PLLBCLK

ADC

ADC Rate

Select

ADC_RATE (R29[7:5])

PAIFTX_LRCLK

SAIF_LRCLK (MFP7)

ADC_CLK

Tie

00,01,11

Tie

ADC_CLKSEL(R8[3:2])

SPDIFRX_EN

ADC_CLKSEL_I

If the S/PDIF Rx is enabled, then ADC_CLK is

forced to ADCMCLK (when ADC_CLKSEL =

00,01 or 10) or ADC_CLK is forced to MCLK pin

(when ADC_CLKSEL=11)

If the S/PDIF Rx is disabled then

ADC_CLKSEL controls the

ADC_CLK clock selection

ADC_RATE_SEL

Figure 27 ADC Clock and ADC Rate Selection

The sample rate at which the ADC operates is determined by the ADC Rate module. Which is part of

the ADC. The ADC rate module divides down the ADC_CLK and calculates the rate at which the

ADC operates based on the ADC_CLK, the ADC_RATE and the digital routing setup. These 3 things

combine to generate the ADC_RATE_SEL. Table 36 summerises the sample rate selection based

on what sources the ADC output.

ADC Data Destination

Clock used for ADC

rate Generator (fs)

Comments

PAIFTX =ADC

PAIFTX_LRCLK

ADC sample rate based on PAIF Tx

SAIFTX =ADC

SAIF_LRCLK

Assumes that PAIF sources another

interface then ADC sample rate based on

SAIF Tx

S/PDIFTX =ADC

ADC_RATE

ADC sample rate determined by the

ADC_RATE register bits R29,bits 7:5

Table 36 ADC Rate Selection

The ADC_CLK clock source can be independent from the DACs and PLLs, however for

optimum performance it is recommended that clock sources on the WM8580 are

synchronous. If this condition is not met performance may be degraded.

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