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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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WM8580 датащи(PDF) 47 Page - Wolfson Microelectronics plc |
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WM8580 датащи(HTML) 47 Page - Wolfson Microelectronics plc |
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47 / 103 page  Production Data WM8580 w PD Rev 4.5 February 2008 47 S/PDIF INTERFACES The TX_CLKSEL register selects S/PDIF Transmitter clock, TX_CLK, from ADCMCLK, PLLACLK, PLLBCLK, or MCLK. Figure 28 illustrates how the clock is selected. The S/PDIF Receiver only uses PLLACLK, but both PLLACLK and PLLBCLK are unavailable in user mode when the S/PDIF receiver is active. If the digital routing is configured such that the S/PDIF Transmitter is sourcing the S/PDIF Receiver, then PLLACLK is automatically selected. Figure 28 S/PDIF TX Clock and Rate Selection The rate at which the S/PDIF Transmitter operates is determined by the S/PDIF transmitter rate module which is part of the S/PDIF Tx interface. The transmitter rate module calculates the rate based on the digital routing setup. Table 38 summerises the sample rate selection based on the S/PDIFTx interface source data. S/PDIF Tx Data Source Clock used for S/PDIF rate Generator (fs) Comments S/PDIF Tx = S/PDIF RX SFRM_CLK S/PDIF Tx sample rate based on S/PDIF Rx S/PDIF Tx = PAIF RX PAIFRX_LRCLK S/PDIF Tx sample rate based on PAIF Rx S/PDIF Tx = SAIF RX SAIFRX_LRCLK S/PDIF Tx sample rate based on SAIF Rx S/PDIF Tx = ADC PAIFTX_LRCLK or the ADC_RATE PAIFTX_LRCLK if PAIFTX also sources the ADC. ADC_RATE register otherwise. Table 38 S/PDIF Tx Rate Selection |
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