WM8580 datasheet(44/103 Pages) WOLFSON

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WM8580

Production Data

PD Rev 4.5 February 2008

DAC Data Source

Clock used for DAC

rate Generator (fs)

Comments

DAC1 =PAIFRX

PAIFRX_LRCLK

DAC sample rate based on PAIF Rx

DAC1=SAIFRX

SAIFRX_LRCLK

DAC sample rate based on SAIF Rx

DAC1=S/PDIFRX

(DAC2/3 also used)

SFRM_CLK or

PAIFRX_LRCLK

RX2DAC_MODE bit selects between the

SFRM_CLK (default) and the

PAIFRX_LRCLK.

DAC1=S/PDIFRX

(DAC2/3 NOT used)

SFRM_CLK

Set RX2DAC_MODE=0

DAC1=S/PDIFRX

DAC 2/3 = PAIFRX

PAIFRX_LRCLK

Need to synchronise the DACs to use the a

common LRCLK.Set RX2DAC_MODE=1

and S/PDIF Rx sampling rate must be

synchronous to PAIF_LRCLK

Table 34 DAC Sample Rate Selection

If DACs 2 and 3 source the PAIFRX, while DAC 1 sources the S/PDIFRx then to synchronize all

DACs together, the DAC rate generator needs to use a common LRCLK. In this case, the

PAIFRX_LRCLK should be used. This is done by setting register bit RX2DAC_MODE=1, allowing the

PAIF_LRCLK to be used to generate the sampling rate. In this case, the S/PDIF sampling rate must

be synchronised with PAIF_LRCLK. In addition, when using the S/PDIF receiver, the PLLACLK and

PLLBCLK are not available to the DACs, and the DAC_CLK applied to the DACs must be at a

standard audio rate.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

CLKSEL

08h

1:0

DAC_CLKSEL

DAC clock source

00 = MCLK pin

01 = PLLACLK

10 = PLLBCLK

11 = MCLK pin

R15

DAC

Control 1

0Fh

RX2DAC_MODE

DAC oversampling rate and power down

control (only valid when DAC_SRC = 00,

DAC1 data sourced from S/PDIF receiver)

0 = SFRM_CLK determines

oversampling rate, DACs 2/3 powered

down

1 = PAIFRX_LRCLK determines

oversampling rate, DACs 2/3 source

PAIF Receiver

Table 35 DAC Clock Control

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