WM8580 datasheet(43/103 Pages) WOLFSON

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Production Data

WM8580

PD Rev 4.5 February 2008

It is possible to override any autoconfiguration of clocks, allowing the user to manually select an

available clock for a particular interface using the appropriate CLKSEL register bits. The

autoconfiguration can be overridden using the CLKSEL_MAN bit (Reg6, bit 6). Great care must to

used when overriding autoconfigured clocking.This is described in Manual Clock Selection section.

The sample rate at which the DAC, ADC and S/PDIF interfaces operate is configurable. The rate of

operation is determined by the available LRCLK at the interface and how the interface is configured –

master or slave mode. The available options are described in the sections which follow.

The PAIF and SAIF generate a BLCK and LRCLK if in master mode. In slave mode they use the

clocks from input pins.

DAC INTERFACE

The DACs are driven from an internal clock called the DAC_CLK. The DAC_CLKSEL bits (reg8, bits

1:0) select a clock to drive the DAC and the possible sources of DAC_CLK are MCLK, PLLACLK or

PLLBCLK. The digital routing can override the programmed DAC_CLKSEL register bits. For

example, if DAC1 is sourcing the S/PDIF Receiver, then PLLACLK is automatically selected as the

DAC_CLK. Figure 26 illustrates the DAC clock selection and the DAC Rate selection (see next

section).

Figure 26 DAC Clock and DAC Rate Selection

DAC RATE SELECTION

The sampling rate at which a DAC operates is determined by the DAC rate module, which is part of

the DAC. The DAC rate module divides down the DAC_CLK and calculates the rate at which the

DAC operates based on the DAC_CLK and the DAC_RATE_SEL (refer to Figure 26). The

DAC_RATE_SEL is generated based on the digital routing setup, and selects between

128/192/256/384/512/768/1152fs.Table 34 describes which clock is used to calculate the DAC rate.

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