RX72N datasheet(10/179 Pages) RENESAS

10 / 179 page

RX72N Group

1. Overview

R01DS0343EJ0120 Rev.1.20

Page 10 of 179

Nov 15, 2023

Extended serial sound interface (SSIE)

 2 channels

 Full-duplex transmission (only for channel 0)

 Various types of serial audio formatting are supported.

 Master and slave operations are supported.

 The bit-clock frequency is selectable from among 13 frequencies (1/1, 1/2, 1/4, 1/6, 1/8,

1/12, 1/16, 1/24, 1/32, 1/48, 1/64, 1/96, or 1/128).

 Data formats with 8, 16, 18, 20, 22, 24, and 32 bits are supported.

 32-stage FIFO buffers for transmission and reception

 Stopping or not stopping the SSILRCK signal on stopping of data transmission is

selectable.

SD host interface (SDHI)

 1 channel

 Transfer speed: Supports high-speed mode (25 MB/s) and default speed mode

(12.5 MB/s)

 One interface for SD memory and I/O cards (supporting 1- and 4-bit SD buses)

 SD specifications

Part 1: Physical Layer Specification Ver. 3.01 compliant (DDR not supported)

Part E1: SDIO Specification Ver. 3.00

 Error checking: CRC7 for commands and CRC16 for data

 Interrupt requests: Card access interrupt, SDIO access interrupt, card detection

interrupt, interrupt of SD buffer access

 DMA transfer requests: SD_BUF write and SD_BUF read

 Support for card detection and write protection

MMC host interface (MMCIF)

 1 channel

 Transfer speed: Data transfer mode (30 MB/s), backward compatible mode (25 MB/s)

 Compliant with JEDEC STANDARD JESD84-A441 (DDR is not supported)

 Interface for Multimedia Cards (MMCs)

 Data buses: Support for 1-, 4-, and 8-bit MMC buses

 Interrupt requests: Card detection interrupt, error/timeout interrupt, normal operation

interrupt, interrupt of MMCIF buffer access

 DMA transfer requests: CE_DATA write and CE_DATA read

 Support for card detection, boot operation, high priority interrupt (HPI)

The arithmetic unit for trigonometric

functions (TFU)

 Sine, cosine, arctangent,

Simultaneous calculation of sine and cosine

Simultaneous calculation of arctangent and

Parallel data capture unit (PDC)

 1 channel

 Acquisition of synchronization through external 8-bit horizontal and vertical

synchronization signals

 Setting of the image size when clipping of the output for a one-frame image is required

Graphic-LCD controller (GLCDC)

 1 channel

 Various data formats and LCD panels are supported

 Superposition of 3 planes (single-color background, graphic 1, graphic 2)

 32- and 16-bpp graphics data and 8-, 4-, and 1-bit CLUT data formats are supported

2D drawing engine (DRW2D)

 1 channel

 Vector drawing (straight lines, triangles, and circles)

 Bit blitting (with support for filling, copying, stretching, and rotation)

 Bus master function for input and output of frame buffer data

32-, 16-, and 8-bit pixel graphics data are supported

 Bus master function for input of texture data

Input of texture data (32, 24, 16, 8, 4, 2, or 1 bit) are supported.

Run length encoding is supported

A CLUT is installed and index data can be converted into color data

 Two rendering modes are supported (register mode and display list mode)

 Performance counting

 Interrupts in response to completion of rendering and processing of the display list

Table 1.1

Outline of Specifications (9/11)

Classification

Module/Function

Description

x2 y2

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