RX72N datasheet(7/179 Pages) RENESAS

7 / 179 page

RX72N Group

1. Overview

R01DS0343EJ0120 Rev.1.20

Page 7 of 179

Nov 15, 2023

Timers

General PWM timer

(GPTW)

 32 bits × 4 channels (GPTW0 to GPTW3)

 Counting up or down (sawtooth-wave), counting up and down (triangle-wave) selectable

for all channels

 Clock sources independently selectable for each channel

 2 input/output pins per channel

 2 output compare/input capture registers per channel

 For the 2 output compare/input capture registers of each channel, 4 registers are

provided as buffer registers and are capable of operating as comparison registers when

buffering is not in use.

 In output compare operation, buffer switching can be at crests or troughs, enabling the

generation of laterally asymmetrically PWM waveforms.

 Registers for setting up frame intervals on each channel (with capability for generating

interrupts on overflow or underflow)

 Generation of dead times in PWM operation

 Capable of synchronous start, stop, or clearing of counter for any channel

 Capable of a start, stop, clearing, or up-/down-counting of the counter supporting input

level comparison

 Capable of a start, stop, clearing, or up-/down-counting of the counter supporting

maximum of 4 external triggers

 Output pin disabling function by a dead time error or a short circuit detection among

output pins

 Capable of generating conversion start triggers for the A/D converters as well as

monitoring external pins for a start timing of conversion.

 Capable of outputting events, such as compare-match from A to F and overflow/

underflow, to ELC

 Capable of using noise filter of input capture

Port output enable for

GPTW (POEG)

 Controlling the output disable for GPTW waveform output

 Initiation by input level detection of GTETRG pins

 Initiation by output disable request from GPTW

 Initiation by detection of oscillation stop or by software

Programmable pulse

generator (PPG)

 (4 bits × 4 groups) × 2 units

 Pulse output with the MTU or TPU output as a trigger

 Maximum of 32 pulse-output possible

8-bit timers (TMR)

 (8 bits × 2 channels) × 2 units

 Select from among seven internal clock signals (PCLKB/1, PCLKB/2, PCLKB/8,

PCLKB/32, PCLKB/64, PCLKB/1024, PCLKB/8192) and one external clock signal

 Capable of output of pulse trains with desired duty cycles or of PWM signals

 The 2 channels of each unit can be cascaded to create a 16-bit timer

 Generation of triggers for A/D converter conversion

 Capable of generating baud-rate clocks for SCI5, SCI6, and SCI12

 Event linking by the ELC

Compare match timer

(CMT)

 (16 bits × 2 channels) × 2 units

 Select from among four internal clock signals (PCLKB/8, PCLKB/32, PCLKB/128,

PCLKB/512)

Compare match timer W

(CMTW)

 (32 bits × 1 channel) × 2 units

 Compare-match, input-capture input, and output-comparison output are available.

 Select from among four internal clock signals (PCLKB/8, PCLKB/32, PCLKB/128,

PCLKB/512)

 Interrupt requests can be output in response to compare-match, input-capture, and

output-comparison events.

 Event linking by the ELC

Realtime clock (RTCd)*1

 Clock sources: Main clock, sub-clock

 Selection of the 32-bit binary count in time count/second unit possible

 Clock and calendar functions

 Interrupt sources: Alarm interrupt, periodic interrupt, and carry interrupt

 Battery backup operation

 Time-capture facility for three values

 Event linking by the ELC

Watchdog timer (WDTA)

 14 bits × 1 channel

 Select from among 6 counter-input clock signals (PCLKB/4, PCLKB/64, PCLKB/128,

PCLKB/512, PCLKB/2048, PCLKB/8192)

Table 1.1

Outline of Specifications (6/11)

Classification

Module/Function

Description

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