RX72N datasheet(3/179 Pages) RENESAS

3 / 179 page

RX72N Group

1. Overview

R01DS0343EJ0120 Rev.1.20

Page 3 of 179

Nov 15, 2023

Memory

Code flash memory

 Capacity: 2 Mbytes/4 Mbytes

 ROM cache: 8 Kbytes

 120 MHz ≤ No-wait cycle access,

120 MHz > One-wait cycle access

 Instructions hitting the ROM cache or operand = 240 MHz: No-wait access

 On-board programming: Four types

 Off-board programming (parallel programmer mode)

 Instructions are executable only for the program stored in the TM target area by using

the Trusted Memory (TM) function and protection against data reading is realized.

 A dual-bank structure allows programming during reading or exchanging the start-up

areas

Data flash memory

 Capacity: 32 Kbytes

 Programming/erasing: 100,000 times

Unique ID

 16-byte unique ID for each device

RAM

 Capacity: 512 Kbytes

 Up to 240 MHz, no-wait access

Expansion RAM

 Capacity: 512 Kbytes

 120 MHz ≤ No-wait cycle access,

120 MHz > One-wait cycle access

ECC RAM

 Capacity: 32 Kbytes

 If the operating frequency is no greater than 120 MHz, one-wait cycle access,

if greater than 120MHz, two-wait cycle access in the case of reading, and three-wait

cycle access in the case of writing

 SEC-DED (single-bit error correction and double-bit error detection)

Standby RAM

 Capacity: 8 Kbytes

 Operation synchronized with PCLKB: Up to 60 MHz, two-cycle access

Operating modes

 Operating modes by the mode-setting pins at the time of release from the reset state

Single-chip mode

Boot mode (for the SCI interface)

Boot mode (for the USB interface)

Boot mode (for the FINE interface)

 Selection of operating mode by register setting

Single-chip mode

On-chip ROM disabled extended mode

On-chip ROM enabled extended mode

 Endian selectable

Clock

Clock generation circuit

 Main clock oscillator, sub-clock oscillator, low-speed/high-speed on-chip oscillator, PLL

frequency synthesizer (two circuits), and IWDT-dedicated on-chip oscillator

 The peripheral module clocks can be set to frequencies above that of the system clock.

 Main-clock oscillation stoppage detection

 Separate frequency-division and multiplication settings for the system clock (ICLK),

peripheral module clocks (PCLKA, PCLKB, PCLKC, PCLKD), flash-IF clock (FCLK) and

external bus clock (BCLK)

The CPU and other bus masters run in synchronization with the system clock (ICLK): Up

to 240 MHz

Peripheral modules of MTU, RSPI, SCIi, ETHERC, EPTPC, PMGI, EDMAC, GPTW,

GLCDC, and DRW2D, run in synchronization with PCLKA, which operates at up to 120

MHz.

Other peripheral modules run in synchronization with PCLKB: Up to 60 MHz

ADCLK in the S12AD (unit 0) runs in synchronization with PCLKC: Up to 60 MHz

ADCLK in the S12AD (unit 1) runs in synchronization with PCLKD: Up to 60 MHz

Flash IF run in synchronization with the flash-IF clock (FCLK): Up to 60 MHz

Devices connected to the external bus run in synchronization with the external bus clock

(BCLK): Up to 80 MHz

 The high-speed on-chip oscillator (HOCO) can be obtained through frequency-

multiplication of the PLL or PPLL reference clock

 External clock input frequency: 30 MHz (max)

 Clock output function

Table 1.1

Outline of Specifications (2/11)

Classification

Module/Function

Description

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