RX72N datasheet(4/179 Pages) RENESAS

4 / 179 page

RX72N Group

1. Overview

R01DS0343EJ0120 Rev.1.20

Page 4 of 179

Nov 15, 2023

Reset

Nine types of reset

 RES# pin reset: Generated when the RES# pin is driven low.

 Power-on reset: Generated when the RES# pin is driven high and VCC = AVCC0 =

AVCC1 rises.

 Voltage-monitoring 0 reset: Generated when VCC = AVCC0 = AVCC1 falls.

 Voltage-monitoring 1 reset: Generated when VCC = AVCC0 = AVCC1 falls.

 Voltage-monitoring 2 reset: Generated when VCC = AVCC0 = AVCC1 falls.

 Deep software standby reset: Generated in response to an interrupt to trigger release

from deep software standby.

 Independent watchdog timer reset: Generated when the independent watchdog timer

underflows, or a refresh error occurs.

 Watchdog timer reset: Generated when the watchdog timer underflows, or a refresh

error occurs.

 Software reset: Generated by register setting.

Power-on reset

 If the RES# pin is at the high level when power is supplied, an internal reset is

generated.

After VCC = AVCC0 = AVCC1 has exceeded the voltage detection level and the

specified period has elapsed, the reset is cancelled.

Voltage detection circuit (LVDA)

Monitors the voltage being input to the VCC = AVCC0 = AVCC1 pins and generates an

internal reset or interrupt.

 Voltage detection circuit 0

Capable of generating an internal reset

The option-setting memory can be used to select enabling or disabling of the reset.

Voltage detection level: Selectable from three different levels (2.94 V, 2.87 V, 2.80 V)

 Voltage detection circuits 1 and 2

Voltage detection level: Selectable from three different levels (2.99 V, 2.92 V, 2.85 V)

Digital filtering (1/2, 1/4, 1/8, and 1/16 LOCO frequency)

Capable of generating an internal reset

 Two types of timing are selectable for release from reset

An internal interrupt can be requested.

 Detection of voltage rising above and falling below thresholds is selectable.

 Maskable or non-maskable interrupt is selectable

Voltage detection monitoring

Event linking

Low power

consumption

Low power consumption

function

 Module stop function

 Four low power consumption modes

Sleep mode, all-module clock stop mode, software standby mode, and deep software

standby mode

Battery backup function

 When the voltage on the VCC pin drops, battery power from the VBATT pin is supplied

to keep the real-time clock (RTC) operating.

Interrupt

Interrupt controller

(ICUD)

 Number of interrupt vectors: 256

 External interrupts: 16 (pins IRQ0 to IRQ15)

 Software interrupts: 2 sources

 Non-maskable interrupts: 8 sources

 Sixteen levels specifiable for the order of priority

 Method of interrupt source selection:

The interrupt vectors consist of 256 vectors (128 sources are fixed. The remaining 128

vectors are selected from among the other 163 sources.)

External bus extension

 The external address space can be divided into eight areas (CS0 to CS7), each with

independent control of access settings.

Capacity of each area: 16 Mbytes (CS0 to CS7)

A chip-select signal (CS0# to CS7#) can be output for each area.

Each area is specifiable as an 8-, 16-, or 32-bit bus space.

The data arrangement in each area is selectable as little or big endian (only for data).

 SDRAM interface connectable

 Bus format: Separate bus, multiplex bus

 Wait control

 Write buffer facility

Table 1.1

Outline of Specifications (3/11)

Classification

Module/Function

Description

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