RX72N datasheet(8/179 Pages) RENESAS

8 / 179 page

RX72N Group

1. Overview

R01DS0343EJ0120 Rev.1.20

Page 8 of 179

Nov 15, 2023

Timers

Independent watchdog

timer (IWDTa)

 14 bits × 1 channel

 Counter-input clock: IWDT-dedicated on-chip oscillator

 Dedicated clock/1, dedicated clock/16, dedicated clock/32, dedicated clock/64,

dedicated clock/128, dedicated clock/256

 Window function: The positions where the window starts and ends are specifiable (the

window defines the timing with which refreshing is enabled and disabled).

 Event linking by the ELC

Communication

function

Ethernet controller

(ETHERC)

 2 channels

 Input and output of Ethernet/IEEE 802.3 frames

 Transfer at 10 or 100 Mbps

 Full- and half-duplex modes

 MII (Media Independent Interface) and RMII (Reduced Media Independent Interface) as

defined in IEEE 802.3u

 Detection of Magic PacketsTM*2 or output of a “wake-on-LAN” signal (WOL)

 Compliance with flow control as defined in IEEE 802.3x standards

 Filtering of multicast frames is supported.

 Frame data can be directly transferred between 2 channels by cut-through switching.

PHY management

interface (PMGI)

 2 channels

 This module is compliant with the MII (Media Independent Interface) as defined in the

IEEE 802.3u standard.

 Transmission and reception of management frames through PHY-LSI chips having an

MII or RMII interface is supported.

 Alleviates load on the CPU by shifting it to dedicated hardware

 The timing of management data is adjustable.

 Preambles can be deleted.

PTP module for the

ethernet controller

(EPTPCb)

 In connection with the Ethernet controller (ETHERC), this module is compliant with the

IEEE1588 standard.

 Matching with time stamps can be used to trigger counting by the MTU and GPTW.

DMA controller for

ethernet controller

(EDMACa)

 3 channels (each EDMAC determines the order of priority by a round-robin algorithm)

For ETHERC: 2 channels, for EPTPC: 1 channel

 Alleviation of CPU load by the descriptor control method

 Transmission FIFO: 2 Kbytes; Reception FIFO: 4 Kbytes

USB 2.0 FS host/

function module (USBb)

 Includes a UDC (USB Device Controller) and transceiver for USB 2.0 FS

 One port

 Compliance with the USB 2.0 specification

 Transfer rate: Full speed (12 Mbps), low speed (1.5 Mbps) (host only)

 Both self-power mode and bus-power mode are supported

 OTG (On the Go) operation is possible (low-speed is not supported)

 Incorporates 2 Kbytes of RAM as a transfer buffer

 External pull-up and pull-down resistors are not required

Table 1.1

Outline of Specifications (7/11)

Classification

Module/Function

Description

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