RX72N datasheet(9/179 Pages) RENESAS

9 / 179 page

RX72N Group

1. Overview

R01DS0343EJ0120 Rev.1.20

Page 9 of 179

Nov 15, 2023

Communication

function

Serial communications

interfaces

(SCIj, SCIi, SCIh)

 13 channels (SCIj: 7 channels + SCIi: 5 channels + SCIh: 1 channel)

 SCIj, SCIi, SCIh

Serial communications modes: Asynchronous, clock synchronous, and smart-card

interface

Multi-processor function

On-chip baud rate generator allows selection of the desired bit rate

Choice of LSB-first or MSB-first transfer

Start-bit detection: Level or edge detection is selectable.

Simple I2C

Simple SPI

7- to 9-bit transfer mode

Bit rate modulation

Double-speed mode

Detecting matches of data is supported (other than for SCI12)

 SCIj, SCIh

Average transfer rate clock can be input from TMR timers for SCI5, SCI6, and SCI12

Event linking by the ELC (only on channel 5)

 SCIh

Supports the serial communications protocol, which contains the start frame and

information frame

Supports the LIN format

 SCIi

Data can be transmitted or received in sequence by the 16-byte FIFO buffers of the

transmission and reception unit

I2C bus interface (RIICa)

 3 channels (only channel 0 can be used in fast-mode plus)

Communication formats

I2C bus format/SMBus format

Supports the multi-master

Max. transfer rate: 1 Mbps (channel 0)

 Event linking by the ELC

CAN module (CAN)

 3 channels

 Compliance with the ISO11898-1 specification (standard frame and extended frame)

 32 mailboxes per channel

Serial peripheral

interface (RSPIc)

 3 channels

 RSPI transfer facility

Using the MOSI (master out, slave in), MISO (master in, slave out), SSL (slave select),

and RSPCK (RSPI clock) signals enables serial transfer through SPI operation (four

lines) or clock-synchronous operation (three lines)

Capable of handling serial transfer as a master or slave

 Data formats

Switching between MSB first and LSB first

The number of bits in each transfer can be changed to any number of bits from 8 to 16,

or to 20, 24, or 32 bits.

128-bit buffers for transmission and reception

Up to four frames can be transmitted or received in a single transfer operation (with

each frame having up to 32 bits)

Transit/receive data can be swapped in byte units

 Buffered structure

Double buffers for both transmission and reception

 RSPCK can be stopped with the receive buffer full for master reception.

 Event linking by the ELC

Quad serial peripheral

interface (QSPI)

 1 channel

 Connectable with serial flash memory equipped with multiple input and output lines (i.e.

for single, dual, or quad operation)

 Programmable bit length and selectable active sense and phase of the clock signal

 Sequential execution of transfer

 LSB or MSB first is selectable

Table 1.1

Outline of Specifications (8/11)

Classification

Module/Function

Description

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