CMV300 datasheet(22/56 Pages) AMSOSRAM

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Reference:CMV300-datasheet-v2.11

CMV300 Datasheet

Page 20 of 54

4 READING OUT THE SENSOR

When reading out the CMV300, the user has a choice to use 4 LVDS outputs (max 480fps) or 1 parallel CMOS output

(max 120 fps). This choice is made by connecting pin B2 to VDD33 (LVDS outputs) or GND (parallel CMOS output).

4.1 LVDS DATA OUTPUTS

The CMV300 has LVDS (low voltage differential signaling) outputs to transport the image data to the surrounding

system. Next to 4 data channels, the sensor also has two other LVDS channels for control and synchronization of the

image data. In total, the sensor has 6 LVDS output pairs (2 pins for each LVDS channel):



4 Data channels



1 Control channel



1 Clock channel

This means that a total of 12 pins of the CMV300 are used for the LVDS outputs (8 for data + 2 for LVDS clock + 2 for

control channel). See the pin list for the exact pin numbers of the LVDS outputs. The 4 data channels are used to transfer

the 12-bit, 10-bit or 8-bit pixel data from the sensor to the receiver in the surrounding system. The output clock channel

transports a clock, synchronous to the data on the other LVDS channels. This clock can be used at the receiving end to

sample the data. This clock is a DDR clock which means that the frequency will be half of the output data rate. When

480Mbps output data rate is used, the LVDS output clock will be 240MHz. The data on the control channel contains

status information on the validity of the data on the data channels. Information on the control channel is grouped in

12-bit words that are transferred synchronous to the 4 data channels.

4.1.1 LVDS LOW-LEVEL PIXEL TIMING

The figures below show the timing for transfer of 8-bit, 10-bit and 12-bit pixel data over one LVDS output. To make the

timing more clear, the figures show only the p-channel of each LVDS pair. The data is transferred LSB first, with the

transfer of bit D[0] during the high phase of the DDR output clock.

‘0’

D(0)

D(1)

D2)

D(3)

D(4)

D(5)

D(6)

D(7)

‘0'

‘0’

LVDS_CLOCK_OUT

DATA_OUT

‘0’

FIGURE 14: 8-BIT PIXEL DATA ON AN LVDS CHANNEL

‘0’

D(0)

D(1)

D2)

D(3)

D(4)

D(5)

D(6)

D(7)

D(8)

D(9)

‘0’

LVDS_CLOCK_OUT

DATA_OUT

D(0)

D(1)

FIGURE 15: 10-BIT PIXEL DATA ON AN LVDS CHANNEL

D(0)

D(1)

D2)

D(3)

D(4)

D(5)

D(6)

D(7)

D(8)

D(9)

LVDS_CLOCK_OUT

DATA_OUT

D(10) D(11) D(0)

D(1)

D2)

D(3)

FIGURE 16: 12-BIT PIXEL DATA ON AN LVDS CHANNEL

The time ‘T1’ in the diagram above is 1/12th of the period of the input clock (CLK_IN) of the CMV300. If a frequency of

40MHz is used for CLK_IN (max), this results in a 240MHz LVDS_CLOCK_OUT.

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