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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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CMV300 датащи(PDF) 48 Page - ams-OSRAM AG |
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CMV300 датащи(HTML) 48 Page - ams-OSRAM AG |
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48 / 56 page  Reference:CMV300-datasheet-v2.11 CMV300 Datasheet Page 46 of 54 © 2016 CMOSIS bvba 9 PIN LIST A distinction is made when the sensor is used in LVDS output mode or in parallel CMOS output mode. 9.1 LVDS OUTPUT MODE PIN LIST The pin list of the CMV300 in LVDS output mode can be found below. Pin number Pin name Description Block Type A1 Test1 No need to connect Sequencer Test pin A2 GND Connect to GND GND A3 GND Connect to GND GND A4 VDDpix Connect to 3.0V supply Pixel array Supply A5 GND Connect to GND GND A6 Output3_P Image data output LVDS Output A7 Output4_P Image data output LVDS Output A8 SPI_OUT SPI output, 3.3V signaling SPI IO B1 Test2 No need to connect Sequencer Test pin B2 Enable_LVDS Connect to VDD33 Sequencer VDD33 B3 VDD20 Connect to 2.2V supply LVDS, ADC Supply B4 VDD33 Connect to 3.3V supply I/O, SPI, ADC Supply B5 Output3_N Image data output LVDS output B6 Output4_N Image data output LVDS Output B7 Output_clk_P LVDS clock output LVDS output B8 SPI_IN SPI input, 3.3V signaling SPI IO C1 VDD33 Connect to 3.3V supply I/O, SPI, ADC Supply C2 VDDpix Connect to 3.0V supply Pixel array Supply C3 R_adc2 Optional, no need to connect ADC Bias C4 R_adc1 Optional, no need to connect ADC Bias C5 Output_clk_N LVDS clock output LVDS output C6 Test3 No need to connect Sequencer Test C7 SPI_EN SPI input, 3.3V signaling SPI IO C8 GND Connect to GND GND D1 Vref Decouple with 100nF to GND ADC Bias D2 Vramp1 Decouple with 100nF to GND ADC Bias D3 Vramp2 Decouple with 100nF to GND ADC Bias D4 NC Not connected NA D5 NC Not connected NA D6 NC Not connected NA D7 LVDS_CLK_N LVDS input clock (N), optional LVDS Input D8 LVDS_CLK_P LVDS input clock (P), optional LVDS Input E1 CMD_ramp Decouple with with 100nF to VDD33 ADC Bias E2 Vpch_L Decouple with with 100nF to GND Pixel array Bias E3 Vbgap Decouple with with 100nF to GND Pixel array Bias E4 NC Not connected NA E5 NC Not connected NA E6 NC Not connected NA E7 VDD33 Connect to 3.3V supply I/O, SPI, ADC Supply E8 GND Connect to GND GND F1 VDD33 Connect to 3.3V supply I/O, SPI, ADC Supply F2 VDDpix Connect to 3.0V supply Pixel array Supply F3 VDD33 Connect to 3.3V supply I/O, SPI, ADC Supply F4 FRAME_REQ Digital input, 3.3V signaling Sequencer IO F5 Output_ctrl_N LVDS control output LVDS Output F6 T_EXP2 Digital input, 3.3V signaling Sequencer IO F7 CLK_IN Master clock input (max 25MHz), 3.3V signaling Sequencer IO |
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