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Reference:CMV300-datasheet-v2.11

CMV300 Datasheet

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and do not contain useful image data. This means that the useable image data area is 644 x 484. This results in an optical

area of 1/3 optical inch (5.9 mm). This means that off-the-shelf C-mount lenses can be used.

2.2 ANALOG FRONT END

The analog front end consists of 2 major parts, a column amplifier block and a column ADC block.

The column amplifier prepares the pixel signal for the column ADC and applies analog gain if desired (programmable

using the SPI interface). The column ADC converts the analog pixel value to a 12 bit value. A digital offset can also be

applied to the output of the column ADC’s. All gain and offset settings can be programmed using the SPI interface.

2.3 LVDS BLOCK

The LVDS block converts the digital data coming from the column ADC into standard serial LVDS data running at

maximum 300Mbps. The sensor has 6 LVDS output pairs:



4 Data channels



1 Control channel



1 Clock channel

The 4 data channels are used to transfer 12-bit data words from sensor to receiver. The output clock channel transports

a DDR clock, synchronous to the data on the other LVDS channels. This clock can be used at the receiving end to sample

the data. The data on the control channel contains status information on the validity of the data on the data channels,

among other useful sensor status information. Details on the LVDS timing and format can be found in section 4 of this

document.

2.4 PARALLEL CMOS OUTPUT BLOCK

The parallel CMOS block sends the digital data coming from the column ADC to a standard CMOS parallel output

(supplied by VDD20) running at maximum 25MHz. The parallel output has 13 pins:



10 Data channels



2 Control channels



1 Clock channel

The 10 data channels are used to transfer 10-bit pixel data from the sensor to a receiver. The output clock channel

transports a clock, synchronous to the data on the data channels. This clock can be used at the receiving end to sample

the data. The data on the control channels contains status information on the validity of the data on the data channels

(LVAL, DVAL). Details on the parallel CMOS timing and format can be found in section 4 of this document.

2.5 SEQUENCER

The on-chip sequencer will generate all required control signals to operate the sensor from only a few external control

signals. This sequencer can be activated and programmed through the SPI interface. A detailed description of the SPI

registers and sensor (sequencer) programming can be found in section 5 of this document.

2.6 SPI INTERFACE

The SPI interface is used to load the sequencer registers with data. The data in these registers is used by the sequencer

while driving and reading out the image sensor. Features like windowing, subsampling, gain and offset are programmed

using this interface. The data in the on-chip registers can also be read back for test and debug of the surrounding system.

Section 5 contains more details on register programming.

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