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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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RA4E1 датащи(PDF) 75 Page - Renesas Technology Corp |
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RA4E1 датащи(HTML) 75 Page - Renesas Technology Corp |
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75 / 81 page  Table A3.1 Peripheral base address (2 of 2) Name Description Base address IIC0WU Inter-Integrated Circuit 0 Wake-up Unit 0x4009_F014 CAN0 CAN0 Module 0x400A_8000 PSCU Peripheral Security Control Unit 0x400E_0000 AGT0 Low Power Asynchronous General purpose Timer 0 0x400E_8000 AGT1 Low Power Asynchronous General purpose Timer 1 0x400E_8100 AGT2 Low Power Asynchronous General purpose Timer 2 0x400E_8200 AGT3 Low Power Asynchronous General purpose Timer 3 0x400E_8300 AGT5 Low Power Asynchronous General purpose Timer 5 0x400E_8500 CRC CRC Calculator 0x4010_8000 DOC Data Operation Circuit 0x4010_9000 SCI0 Serial Communication Interface 0 0x4011_8000 SCI3 Serial Communication Interface 3 0x4011_8300 SCI4 Serial Communication Interface 4 0x4011_8400 SCI9 Serial Communication Interface 9 0x4011_8900 SPI0 Serial Peripheral Interface 0 0x4011_A000 SCE9 Secure Cryptographic Engine 0x4016_1000 GPT321 General PWM 32-Bit Timer 1 0x4016_9100 GPT322 General PWM 32-Bit Timer 2 0x4016_9200 GPT164 General PWM 16-Bit Timer 4 0x4016_9400 GPT165 General PWM 16-Bit Timer 5 0x4016_9500 ADC120 12bit A/D Converter 0 0x4017_0000 DAC12 12-bit D/A converter 0x4017_1000 FLAD Data Flash 0x407F_C000 FACI Flash Application Command Interface 0x407F_E000 QSPI Quad-SPI 0x6400_0000 Note: Name = Peripheral name Description = Peripheral functionality Base address = Lowest reserved address or address used by the peripheral 3.2 Access Cycles This section provides access cycle information for the I/O registers described in this manual. ● Registers are grouped by associated module. ● The number of access cycles indicates the number of cycles based on the specified reference clock. ● In the internal I/O area, reserved addresses that are not allocated to registers must not be accessed, otherwise operations cannot be guaranteed. ● The number of I/O access cycles depends on bus cycles of the internal peripheral bus, divided clock synchronization cycles, and wait cycles of each module. Divided clock synchronization cycles differ depending on the frequency ratio between ICLK and PCLK. ● When the frequency of ICLK is equal to that of PCLK, the number of divided clock synchronization cycles is always constant. ● When the frequency of ICLK is greater than that of PCLK, at least 1 PCLK cycle is added to the number of divided clock synchronization cycles. ● The number of write access cycles indicates the number of cycles obtained by non-bufferable write access. RA4E1 Datasheet Appendix 3. I/O Registers R01DS0391EJ0130 Rev.1.30 Jun 6, 2025 Page 75 of 81 |
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