M7020R datasheet(126/150 Pages) STMICROELECTRONICS

126 / 150 page

M7020R

126/150

SRAM ADDRESSING

Table 50, page 127 describes the commands used

to generate addresses on the SRAM Address Bus.

The index [14:0] field contains the address of a 68-

bit entry that results in a hit in 68-bit-configured

quadrant. It is the address of the 68-bit entry that

lies at the 136-bit page, and the 272-bit page

boundaries in 136-bit- and 272-bit-configured

quadrants, respectively.

REGISTERS, page 21 of this specification, de-

scribes the NFA and SSR Registers. ADR[14:0]

contains the address supplied on the DQ Bus dur-

ing PIO access to the M7020R. Command Bits 8

and 7 {CMD[8:7]} are passed from the command

to the SRAM Address Bus (see COMMAND

CODES AND PARAMETERS, page 29 for more

information). ID[4:0] is the ID of the device driving

the SRAM Bus (see Figure 3, page 10 and Table

2, page 9 for more information).

SRAM PIO Access

SRAM READ enables READ access to off-chip

SRAM that contains associative data. The latency

from the issuance of the READ Instruction to the

address appearing on the SRAM Bus is the same

as the latency of the SEARCH Instruction and will

depend on the TLSZ value parameter pro-

grammed in the device Configuration Register.

The latency of the ACK from the READ Instruction

is the same as the latency of the SEARCH Instruc-

tion to the SRAM address plus the HLAT pro-

grammed in the Configuration Register.

Note: SRAM READ is a blocking operation – no

new instruction can begin until the ACK is returned

by the selected device performing the access.

SRAM WRITE enables WRITE access to the off-

chip SRAM containing associative data. The laten-

cy from the second cycle of the WRITE Instruction

to the address appearing on the SRAM Bus is the

same as the latency of the SEARCH Instruction

and will depend on the TLSZ value parameter pro-

grammed in the device Configuration Register.

Note: SRAM WRITE is a pipelined operation –

new instruction can begin right after the previous

command has ended.

SRAM READ with a Table of One Device

SRAM READ enables READ access to the off-

chip SRAM containing associative data. The laten-

cy from the issuance of the READ Instruction to

the address appearing on the SRAM Bus is the

same as the latency of the SEARCH Instruction

and will depend on the TLSZ value parameter pro-

grammed in the device configuration register. The

latency of the ACK from the READ Instruction is

the same as the latency of the SEARCH Instruc-

tion to the SRAM address plus the HLAT pro-

grammed in the configuration register.

The following explains the SRAM READ operation

in a table with only one device that has the follow-

ing parameters: TLSZ = 00, HLAT = 000, LRAM =

1, and LDEV = 1. Figure 93, page 127 shows the

associated timing diagram.

For the following description, the selected device

refers to the only device in the table because it is

the only device to be accessed.

The sequence of the operation is as follows:

– Cycle 1A: The host ASIC applies the READ In-

struction on the CMD[1:0], using CMDV = 1.

The

Bus

supplies

the

address

with

DQ[20:19] set to '10' to select the SRAM ad-

dress. The host ASIC selects the device for

which the ID[4:0] matches the DQ[25:21] lines.

During this cycle, the host ASIC also supplies

SADR[21:20] on CMD[8:7] in this cycle.

– Cycle 1B: The host ASIC continues to apply the

READ Instruction on the CMD[1:0] using

CMDV = 1. The DQ Bus supplies the address

with DQ[20:19] set to '10' to select the SRAM

address.

– Cycle 2: The host ASIC floats DQ[67:0] to a 3-

state condition.

– Cycle 3: The host ASIC keeps DQ[67:0] in a 3-

state condition.

– Cycle 4: The selected device starts to drive

DQ[67:0] and drives ACK from High-Z to low.

– Cycle 5: The selected device drives the READ

address on SADR[21:0]; it also drives ACK high,

CE_L low, and ALE_L low.

– Cycle 6: The selected device drives CE_L high,

ALE_L high, the SADR Bus, and the DQ Bus in

a 3-state condition; it drives ACK low.

At the end of Cycle 6, the selected device floats

ACK in a 3-state condition, and a new command

can begin.

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