M7020R datasheet(19/150 Pages) STMICROELECTRONICS

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M7020R

CONNECTION DESCRIPTIONS

Clocks and Reset

Master Clock (CLK2X). M7020R samples all the

data and control pins on the positive edge of

CLK2X. All signals are driven out of the device on

the rising edge of CLK2X (when PHS_L is low).

Phase (PHS_L). This signal runs at half the fre-

quency of CLK2X and generates an internal CLK

from CLK2X see Figure 9, page 20.

Test Input (TEST - for Cypress Semiconductor

Use Only). This signal should be connected to

ground.

Reset (RST_L). Driving RST_L low initializes the

device to a known state.

CMD and DQ Bus

CMD Bus (CMD[8:0]. [1:0] specifies the com-

mand; [8:2] contains the CMD parameters. The

descriptions of individual commands explains the

details of the parameters. The encoding of com-

mands based on the [1:0] field are:

– 00: PIO READ

– 01: PIO WRITE

– 10: SEARCH

–11: LEARN

CMD Valid (CMDV). Qualifies the CMD bus:

– 0: No Command

– 1: Command

Address/Data Bus (DQ[67:0]). This signal carries

the READ and WRITE address and data during

ries the compare data during SEARCH opera-

tions. It also carries the SRAM address during

SRAM PIO accesses.

READ Acknowledge (ACK). This

signal

indi-

cates that valid data is available on the DQ Bus

during register, data, and mask array READ oper-

ations, or the data is available on the SRAM data

bus during SRAM READ operations.

Note: ACK Signals require a weak external pull-

down resistor such as 47 or 100 K

Ω.

End of Transfer (EOT). This signal indicates the

end of burst transfer to the data or mask array dur-

ing READ or WRITE burst operations.

Note: EOT Signals require a weak external pull-

down resistor such as 47 K

Ω or 100 KΩ.

SEARCH Successful Flag (SSF). When assert-

ed, this signal indicates that the device is the glo-

bal winner in a SEARCH operation.

SEARCH Successful Flag Valid (SSV). When

asserted, this signal qualifies the SSF signal.

SRAM Interface

SRAM Address (SADR[21:0]). This

bus

con-

tains address lines to access off-chip SRAMs that

contain associative data. See Table 50, page 127

for the details of the generated SRAM address. In

a database of multiple M7020Rs, each corre-

sponding bit of SADR from all cascaded devices

must be connected.

SRAM Chip Enable (CE_L). This is chip enable

control for external SRAMs. In a database of mul-

tiple M7020Rs, CE_L of all cascaded devices

must be connected. This signal is then driven by

only one of the devices.

SRAM Write Enable (WE_L). This is write en-

able control for external SRAMs. In a database of

multiple M7020Rs, WE_L of all cascaded devices

must be connected together. This signal is then

driven by only one of the devices.

SRAM Output Enable (OE_L). This is output en-

able control for external SRAMs. Only the last de-

vice drives this signal (with the LRAM bit set).

Address Latch Enable (ALE_L). When this sig-

nal is low, the addresses are valid on the SRAM

Address Bus. In a database of multiple M7020Rs,

the ALE_L of all cascaded devices must be con-

nected. This signal is then driven by only one of

the devices.

Cascade Interface

Local Hit In (LHI[6:0]). These

pins depth-cas-

cade the device to form a larger table size. One

signal of this bus is connected to the LHO[1] or

LHO[0] of each of the upstream devices in a block.

All unused LHI pins are connected to a logic '0.'

(For more information, see DEPTH-CASCADING,

page 122.)

Local Hit Out (LHO[1:0]). LHO[1] and

LHO[0]

are the same logical signal. LHO[1] or LHO[0] is

connected to one input of the LHI bus of up to four

downstream devices in a block of up to eight de-

vices. (For more information, see DEPTH-CAS-

CADING, page 122.)

Block Hit In (BHI[2:0]). Inputs from the previous

BHO[2:0] are tied to the BHI[2:0] of the current de-

vice. In a four-block system, the last block can

contain only seven devices because the ID code

11111 is used for broadcast access.

Block Hit Out (BHO[2:0]). These outputs from

the last device in a block are connected to the

BHI[2:0] inputs of the devices in the downstream

blocks.

Full In (FULI[6:0]). Each signal in this bus is con-

nected to FULO[0] or FULO[1] of an upstream de-

vice to generate the FULL signal for the depth-

cascaded block.

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