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M7020R датащи(PDF) 128 Page - STMicroelectronics |
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M7020R датащи(HTML) 128 Page - STMicroelectronics |
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128 / 150 page ![]() M7020R 128/150 SRAM READ with a Table of Up to Eight Devices The following explains the SRAM READ operation completed through a table of up to eight devices using the following parameters: TLSZ = 01. Figure 94, page 129 diagrams a block of eight devices. The following assumes that SRAM access is suc- cessfully achieved through M7020R Device 0. Fig- ure 95, page 130 and Figure 96, page 131 show timing diagrams for Device 0 and Device 7, re- spectively. – Cycle 1A: The host ASIC applies the READ In- struction on the CMD[1:0] using CMDV = 1. The DQ Bus supplies the address, with DQ[20:19] set to '10' to select the SRAM address. The host ASIC selects the device for which ID[4:0] match- es the DQ[25:21] lines. During this cycle the host ASIC also supplies SADR[21:20] on CMD[8:7]. – Cycle 1B: The host ASIC continues to apply the READ Instruction on the CMD[1:0] using CMDV = 1. The DQ Bus supplies the address with DQ[20:19] set to '10' to select the SRAM address. – Cycle 2: The host ASIC floats DQ[67:0] to a 3- state condition. – Cycle 3: The host ASIC keeps DQ[67:0] in a 3- state condition. – Cycle 4: The selected device starts to drive DQ[67:0]. – Cycle 5: The selected device continues to drive DQ[67:0] and drives ACK from high-Z to low – Cycle 6: The selected device drives the READ address on SADR[21:0]. It also drives ACK high, CE_L low, WE_L high, and ALE_L low. – Cycle 7: The selected device drives CE_L, ALE_L, WE_L, and the DQ Bus in a 3-state con- dition. It continues to drive ACK low. At the end of Cycle 7, the selected device floats ACK in 3-state condition and a new command can begin. |
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