M7020R datasheet(24/150 Pages) STMICROELECTRONICS

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M7020R

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The Command Register

Table 10. Command Register Field Descriptions

Field

Range

Initial Value

Description

SRST

[0]

Software Reset. If ’1,’ this bit resets the device, with the same effect

as the hardware reset. Internally, it generates a reset pulse lasting for

eight CLK cycles. This bit automatically resets to a ’0’ the reset cycle

has completed.

DEVE

[1]

Device Enable. If ’0,’ it keeps the SRAM Bus (SADR, WE_L, CE_L,

OE_L, and ALE_L), SSF, and SSV signals in 3-state condition and

forces the cascade interface output signals LHO[1:0] and BHO[2:0] to

’0.’ It also keeps the DQ Bus in input mode. The purpose of this bit is

to make sure that there are no bus contentions when the devices

power up in the system.

TLSZ

[3:2]

Table Size. The host ASIC must program this field to configure the

chips into a table of a certain size. This field affects the pipeline

latency of the SEARCH and LEARN operations as well as the READ

and WRITE accesses to the SRAM (SADR[21:0], CE_L, OE_L,

WE_L, ALE_L, SSV, SSF, and ACK). Once programmed, the search

latency stays constant.

TLSZ

[3:2]

Latency in #

of CLK Cycles

00: 1 device

01: 2-8 devices

10: 9-31 devices

11: Reserved

HLAT

[6:4]

000

Latency of Hit Signals. This field adds latency to the SSF and SSV

signals during SEARCH, and ACK signal during SRAM READ access

by the following number of CLK cycles.

000: 0

100: 4

001: 1

101: 5

010: 2

110: 6

011: 3

111: 7

LDEV

[7]

Last Device in the Cascade. When set, this device is the last device

on the SRAM bus in the depth-cascaded table and is the default driver

for the SSF and SSV signals.

In the event of a SEARCH failure, the device with this bit set drives the

hit signals as follows:

SSF = 0, SSV = 1

During non-SEARCH cycles, the device with this bit set drives the

signals as follows:

SSF = 0, SSV = 0

LRAM

[8]

Last device on this SRAM Bus. When set, this device is the last

device on this SRAM bus in the depth-cascaded table and is the

default driver for the SADR, CE_L, WE_L, and ALE_L signals. In

cycles where no M7020R device in a depth-cascaded table drives

these signals, this device drives the signals as follows:

SADR = 3FFFFF,

CE_L = 1

WE_L = 1

ALE_L = 1

OE_L is always driven by the device for which this bit is set.

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