M7020R datasheet(89/150 Pages) STMICROELECTRONICS

89 / 150 page

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M7020R

The logical 272-bit SEARCH operation is shown in

Figure 65, page 91. The entire table of 272-bit en-

tries is compared to a 272-bit word K that is pre-

sented on the DQ Bus in Cycles A, B, C, and D of

the command using the GMR and local mask bits.

The GMR is the 272-bit word specified by the two

pairs of GMRs selected by the GMR Indexes in the

command’s Cycles A and C. The 272-bit word K

that is presented on the DQ Bus in Cycles A, B, C,

and D of the command is compared with each en-

try in the table starting at location “0.” The first

matching entry’s location address, “L,” is the win-

ning address that is driven as part of the SRAM

address on SADR[21:0] lines (see SRAM AD-

DRESSING, page 126).

Note: The matching address is always going to be

location “0” in a four-entry page for a 272-bit

SEARCH (two LSBs of the matching index will be

'00').

The SEARCH command is a pipelined operation

and executes at one-fourth the rate of the frequen-

cy of CLK2X for 272-bit searches in x272-config-

ured tables. The latency of SADR, CE_L, ALE_L,

WE_L, SSV, and SSF from the 272-bit SEARCH

command (measured in CLK cycles) from the

CLK2X cycle that contains the C and D Cycles is

shown in Table 41, page 91.

The latency of a SEARCH from command to

SRAM access cycle is 4 for only a single device in

the table and TLSZ = 00. In addition, SSV and SSF

shift further to the right for different values of

HLAT, as specified in Table 42, page 91.

Figure 63. Hardware Diagram for a Table with One Device

DQ[67:0]

CMDV, CMD[8:0]

SSF, SSV

SRAM

BHI[2:0]

BHO[2:0]

LHO[1]

LHI

3210

M7020R

LHO[0]

654

AI05695

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