AT45DB321E datasheet(12/80 Pages) RENESAS

12 / 80 page

DS-AT45DB321E-8784 Rev. N

Page 12

9/1/23

AT45DB321E Datasheet

Read Commands

By specifying the appropriate opcode, data can be read from the main memory or from either one of the two

SRAM data buffers. The DataFlash supports RapidS protocols for Mode 0 and Mode 3. See the “Detailed Bit-level

Read Waveforms: RapidS Mode 0/Mode 3” on page 69 diagrams for details on the clock cycle sequences for each

mode.

6.1

Continuous Array Read (Legacy Command: E8h Opcode)

By supplying an initial starting address for the main memory array, the Continuous Array Read command can be

used to sequentially read a continuous stream of data from the device by simply providing a clock signal; no

additional addressing information or control signals need to be provided. The DataFlash incorporates an internal

address counter that automatically increments on every clock cycle, allowing one continuous read from memory to

be performed without the need for additional address sequences. To perform a Continuous Array Read using the

standard DataFlash page size (528 bytes), an opcode of E8h must be clocked into the device followed by three

address bytes (which comprise the 24-bit page and byte address sequence) and four dummy bytes. The first 13

bits (PA12 - PA0) of the 23-bit address sequence specify which page of the main memory array to read and the

last 10 bits (BA9 - BA0) of the 23-bit address sequence specify the starting byte address within the page. To

perform a Continuous Array Read using the binary page size (512 bytes), an opcode of E8h must be clocked into

the device followed by three address bytes and four dummy bytes. The first 13 bits (A21 - A9) of the 22-bit

address sequence specify which page of the main memory array to read and the last nine bits (A8 - A0) of the 22-

bit address sequence specify the starting byte address within the page. The dummy bytes that follow the address

bytes are needed to initialize the read operation. Following the dummy bytes, additional clock pulses on the SCK

pin result in data being output on the SO (serial output) pin.

The CS pin must remain low during the loading of the opcode, the address bytes, the dummy bytes, and the

reading of data. When the end of a page in the main memory is reached during a Continuous Array Read, the

device continues reading at the beginning of the next page with no delays incurred during the page boundary

crossover (the crossover from the end of one page to the beginning of the next page). When the last bit in the

main memory array has been read, the device continues reading back at the beginning of the first page of

memory. As with crossing over page boundaries, no delays are incurred when wrapping around from the end of

the array to the beginning of the array.

A low-to-high transition on the CS pin terminates the read operation and tri-state the output pin (SO). The

maximum SCK frequency allowable for the Continuous Array Read is defined by the fCAR1 specification. The

Continuous Array Read bypasses the data buffers and leaves the contents of the buffers unchanged.

Warning: This command is not recommended for new designs.

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