AT45DB321E datasheet(79/80 Pages) RENESAS

79 / 80 page

DS-AT45DB321E-8784 Rev. N

Page 79

9/1/23

AT45DB321E Datasheet

29. Revision History

Rev.

Date

Comments

8784A

08/2012

Initial document release.

8784B

11/2012

Added Legacy Commands table.

Updated to Adesto template.

8784C

6/2013

Updated electrical and power specifications. “Buffer 1 (or 2) Read” moved from group C to Group A in

Operation Mode Summary. Removed references to 2.5 V minimum power supply.

8784D

7/2013

Updated Auto Page Rewrite cycle to 50,000 cumulative page erase/program operations. Corrected

Page Erase and Programming Time specification to 35 ms maximum. Updated DC conditions for VOL,

ICC3 and ICC4. Added reserved part order codes. Changed datasheet status from preliminary to

complete.

8784E

10/2013

Updated spec in Continuous Array Read (1Bh Opcode) to fCAR4. Corrected Low Power Read Option

(up to 15MHz). Corrected Ultra-Deep Power-Down current (400nA typical). Updated spec for Input

High Voltage (Max) to VCC + 0.6V.

8784F

11/2013

Corrected Product ID Values for Byte 2 in Figure 12.1, Table 12.1 and Table 12.2. Corrected Memory

Architecture Diagram, Figure 3-1.

8784G

7/2015

Added Die in Wafer Form package option. Added explanation of Read-Modify-Write command

(Section 6.6).Updated Table 6-4 (Main Memory to Buffer Compare). Added information on Power Up

(Section 15.1). Added footnotes to Tables 14-6 and 14-7. Updated Tables 11-1 and 11-3. Updated

condition description for IUDPD, IDPD, and ISB.

8784H

1/2017

Added patent information.

8784I

6/2017

Added clarification of Absolute Maximum Ratings.

8784J

8/2017

Updated 6 x 8 VDFN package drawing.

8784K

9/2017

Updated maximum page program time specification.

8784L

3/2019

Removed 9CC, 9-ball UBGA package option.

Updated tVCSL time in Table 15-1 from 85 to 105 µs.

8784M

2/2022

Changed company logo to Renesas.

8784N

9/2023

Applied new corporate template to document.

Consolidated the ordering information in Section 27.

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