AT45DB321E datasheet(7/80 Pages) RENESAS

7 / 80 page

DS-AT45DB321E-8784 Rev. N

Page 7

9/1/23

AT45DB321E Datasheet

Pin Configurations and Pinouts

Figure 1. Pinouts

Note: The metal pad on the bottom of the UDFN package is not internally connected to a voltage potential. This

pad can be a “no connect” or connected to GND.

Table 1. Pin Configurations

Symbol

Name and Function

Asserted

State

Type

Chip Select

Asserting the CS pin selects the device. When the CS pin is deasserted, the device is

deselected and normally be placed in the standby mode (not Deep Power-Down mode) and

the output pin (SO) is in a high-impedance state. When the device is deselected, data is not

accepted on the input pin (SI).

A high-to-low transition on the CS pin is required to start an operation and a low-to-high

transition is required to end an operation. When ending an internally self-timed operation such

as a program or erase cycle, the device does not enter the standby mode until the completion

of the operation.

Low

Input

SCK

Serial Clock

This pin is used to provide a clock to the device and is used to control the flow of data to and

from the device. Command, address, and input data present on the SI pin is always latched

on the rising edge of SCK, while output data on the SO pin is always clocked out on the falling

edge of SCK.

—

Input

Serial Input

The SI pin is used to shift data into the device. The SI pin is used for all data input including

command and address sequences. Data on the SI pin is always latched on the rising edge of

SCK. Data present on the SI pin are ignored whenever the device is deselected (CS is

deasserted).

—

Input

Serial Output

The SO pin is used to shift data out from the device. Data on the SO pin is always clocked out

on the falling edge of SCK. The SO pin is in a high-impedance state whenever the device is

deselected (CS is deasserted).

—

Output

SCK

RESET

GND

VCC

8-lead SOIC

Top View

SCK

RESET

GND

VCC

8-pad UDFN and DFN

Top View

(Through Package)

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