50

60

70

80

90

100

ALERT

THERM Limit

THERM Limit - Hysteresis

High Temperature Limit

THERM

110

120

130

140

150

Temperature Conversion Complete

Time

Measured

Temperature

ALERT output

serviced by controller

Figure 7-4. ALERT and THERM Interrupt Operation

50

60

70

80

90

100

THERM2

THERM Limit

THERM Limit - Hysteresis

THERM

110

120

130

140

150

Temperature Conversion Complete

Time

Measured

Temperature

THERM2 Limit

THERM2 Limit - Hysteresis

Figure 7-5. THERM and THERM2 Interrupt

Operation

7.4 Device Functional Modes

7.4.1 Shutdown Mode (SD)

The TMP461-EP shutdown mode enables the user to save maximum power by shutting down all device circuitry

other than the serial interface, and reducing current consumption to typically less than 3μA; see Figure 6-10

(Shutdown Quiescent Current vs Supply Voltage). Shutdown mode is enabled when the SD bit (bit 6) of the

configuration register is high; the device shuts down after the current conversion is finished. When the SD bit is

low, the device maintains a continuous-conversion state.

7.5 Programming

7.5.1 Serial Interface

The TMP461-EP device operates only as a target device on either the two-wire bus or the SMBus. Connections

to either bus are made using the open-drain I/O lines, SDA and SCL. The SDA and SCL pins feature integrated

spike suppression filters and Schmitt triggers to minimize the effects of input spikes and bus noise. The

TMP461-EP device supports the transmission protocol for fast (1kHz to 400kHz), fast-plus (1kHz to 1MHz)

and high-speed (1kHz to 2.17MHz) modes. All data bytes are transmitted MSB first.

7.5.1.1 Bus Overview

The TMP461-EP device is SMBus-interface-compatible. In the SMBus protocol, the device that initiates the

transfer is called a controller, and the devices controlled by the controller are targets. The bus must be controlled

by a controller device that generates the serial clock (SCL), controls the bus access, and generates the start and

stop conditions.

To address a specific device, a start condition is initiated. A start condition is indicated by pulling the data line

(SDA) from a high-to-low logic level when SCL is high. All targets on the bus shift in the target address byte, with

the last bit indicating whether a read or write operation is intended. During the ninth clock pulse, the target being

addressed responds to the controller by generating an acknowledge bit and pulling SDA low.

Data transfer is then initiated and sent over eight clock pulses, followed by an acknowledge bit. During data

transfer, SDA must remain stable when SCL is high. A change in SDA when SCL is high is interpreted as a

control signal.

After all data is transferred, the controller generates a stop condition. A stop condition is indicated by pulling SDA

from low to high when SCL is high.

7.5.1.2 Bus Definitions

The TMP461-EP device is two-wire- and SMBus-compatible. Figure 7-6 and Figure 7-7 illustrate the timing for

various operations on the TMP461-EP device. The bus definitions are as follows:

TMP461-EP

SNIS241 – SEPTEMBER 2025

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