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TMP461 датащи(PDF) 15 Page - Texas Instruments |
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TMP461 датащи(HTML) 15 Page - Texas Instruments |
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15 / 38 page ![]() Bus Idle: Both SDA and SCL lines remain high. Start Data Transfer: A change in the state of the SDA line (from high to low) when the SCL line is high defines a start condition. Each data transfer initiates with a start condition. Stop Data Transfer: A change in the state of the SDA line (from low to high) when the SCL line is high defines a stop condition. Each data transfer terminates with a repeated start or stop condition. Data Transfer: The number of data bytes transferred between a start and stop condition is not limited and is determined by the controller device. The receiver acknowledges the data transfer. Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledge bit. A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable low during the high period of the acknowledge clock pulse. Take setup and hold times into account. On a controller receive, data transfer termination can be signaled by the controller generating a not-acknowledge on the last byte that is transmitted by the target. Frame 1 Two Wire Device Address Byte Frame 2 Pointer Register Byte Host Device Device Frame 3 Data Byte 1 ACK By Device 1 D7 SDA (Continued) SCL (Continued) D6 D5 D4 D3 D2 D1 D0 9 9 SCL … 1 9 1 1 Start By ACK By ACK By SDA 0 0 1 1 0 0 P6 P7 P5 P4 P3 P2 P1 P0 … (1) W / R Stop By Host A. Target address 1001100 is shown. Figure 7-6. Two-Wire Timing Diagram for Write Word Format www.ti.com TMP461-EP SNIS241 – SEPTEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: TMP461-EP |
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