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TMP461 датащи(PDF) 7 Page - Texas Instruments |
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TMP461 датащи(HTML) 7 Page - Texas Instruments |
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7 / 38 page ![]() 6.6 Two-Wire Timing Requirements At –55°C to 125°C and V+ = 1.7V to 3.6V, unless otherwise noted FAST-MODE FAST-MODE PLUS HIGH-SPEED MODE UNIT MIN MAX MIN MAX MIN MAX f(SCL) SCL operating frequency 0.001 0.4 0.001 1.0 0.001 2.17 MHz t(BUF) Bus free time between stop and start condition 1300 500 160 ns t(HDSTA) Hold time after repeated start condition. After this period, the first clock is generated. 600 260 160 ns t(SUSTA) Repeated start condition setup time 600 260 160 ns t(SUSTO) Stop condition setup time 600 260 160 ns t(HDDAT) Data hold time 0 900 0 450 0 150 ns t(SUDAT) Data setup time 100 50 40 ns t(LOW) SCL clock low period 1300 500 320 ns t(HIGH) SCL clock high period 600 260 60 ns tF – SDA Data fall time 300 120 130 ns tF, tR – SCL Clock fall and rise time 300 120 40 ns tR Rise time for SCL ≤ 100 kHz 1000 ns 6.7 Timing Diagrams SCL SDA t (LOW) t R t F t (HDSTA) t (HDSTA) t (HDDAT) t (BUF) t (SUDAT) t (HIGH) t (SUSTA) t (SUSTO) P S S P Figure 6-1. Two-Wire Timing Diagram www.ti.com TMP461-EP SNIS241 – SEPTEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: TMP461-EP |
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