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ADA4356ABCZ датащи(PDF) 56 Page - Analog Devices

номер детали ADA4356ABCZ
подробное описание детали  Programmable Transimpedance, Current to Bits Receiver μModule
PDF  61 Pages
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производитель  AD [Analog Devices]
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Data Sheet
ADA4356
analog.com
Rev. 0
56 of 61
Table 19. LVDS-ANSI/LVDS-IEEE Options
BIT 6
OUTPUT MODE
OUTPUT DRIVER CURRENT
0
LVDS-ANSI (default)
Automatically selected to give proper swing.
1
LVDS-IEEE reduced range link
Automatically selected to give proper swing.
Bits[5:3]—Open
Bit 2—Output Invert
Setting this bit inverts the output bit stream.
Bit 1—Open
Bit 0—Output Format
By default, this bit is set to send the data output in two’s complement format. Clearing this bit to 0 changes the
output mode to offset binary.
Output Adjust (Register 0x15)
The power-on default value of this register is 0x00.
Bits[7:6]—Open
Bits[5:4]—Output Driver Termination
These bits allow the user to select the internal termination resistor.
Bits[3:1]—Open
Bit 0—Output Driver
Bit 0 of the output adjust register controls the drive strength on the LVDS driver of the FCO and DCO outputs only.
The default value setsthe drive to 1×, or the drive can increase to 2× by setting the appropriate channel bit in Register
0x05 and then setting Bit 0, Register 0x15. These features cannot be used with the output driver termination select.
The termination selection takes precedence over the 2× driver strength on FCO and DCO when both the output driver
termination and output driver are selected.
Output Phase (Register 0x16)
The power-on default value of this register is 0x03.
Bit 7—Open
Bits[6:4]—Input Clock Phase Adjust
When the clock divider (Register 0x0B) is used, the applied clock is at a higher frequency than the internal sampling
clock. Bits[6:4] of Register 0x16 determine at which phase the external clock sampling occurs. The input clock phase
adjust is only applicable when the clock divider is used. Selecting a value for Bits[6:4] greater than Register 0x0B,
Bits[2:0] is prohibited. See Table 20.
Bits[3:0]—Output Clock Phase Adjust
For more details, see Table 21.



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