ADA4356ABCZ datasheet(43/61 Pages) AD

43 / 61 page

Data Sheet

ADA4356

analog.com

Rev. 0

43 of 61

The pseudo code sequence for a digital reset is as follows:

1. For a digital reset, write Register 0x08 = 0x03.

2. For the normal operation, write Register 0x08 = 0x00.

Controls

The ADA4356 uses four balls to control various functions of the analog front end. Use the GSEL1 (A5) and GSEL0 (A4)

balls to select TZ (see Table 11), use the VLDEN (F7) ball to enable or disable the internal LDO, and use FSEL (A6) to

select the filter bandwidth for the internal LPF. These control balls must be driven, as these balls have no internal

pull-up or pull-down resistors.

Transimpedance Gain and Performance Controls

Each TZ determines its corresponding maximum linear input current and input referred rms current noise (iN), as

listed in Table 9. The GSEL0 and GSEL1 logic levels define TIA gain setting, as shown in Table 11.

Table 11.Truth Table for GSEL1 and GEL0

GSEL1 (BALL A5)

GSEL0 (BALL A4)

INTERNAL GAIN SELECTION

TRANSIMPEDANCE

4.7kΩ‖133kΩ

TZ = 4.54kΩ

12kΩ‖133kΩ

TZ = 11kΩ

133kΩ

TZ = 133kΩ

Reserved

LDO Enable Controls

The internal 1.8V LDO is controlled via the VLDEN ball. The control signal vs. LDO output are shown in Table 12.

Table 12. LDO Control Signal Truth Table

VLDEN (BALL F7)

VLD (BALL F12)

No output

1.8V

LPF Bandwidth Selection

The ADA4356 uses an internal analog LPF to optimize settling time and noise performance. The LPF is controlled via

the FSEL ball, as shown in Table 13. Consider the input signal pulse-width when choosing the LPF bandwidth.

Table 13. LPF Truth Table

FSEL (BALL A6)

LPF BANDWIDTH (MHz)

100

System Data Interface and Timing

The ADA4356 supports high speed, digital serial outputs. These serial differential outputs are LVDS-compatible data

and clock lanes. These output lanes include the D0AP (A14), D0AN (A13), D1AP (B14), D1AN (B13), DCOP (D14), DCON

(D13), FCOP (C14), and FCON (C13) balls.

At power-on default, the ADA4356 differential outputs conform to the ANSI-644 LVDS standard. Each of the LVDS

output driver currents is set at a nominal 3.5mA. A 100Ω differential termination resistor placed at the LVDS receiver

inputs results in a nominal 350mV swing (or 700mV p-p differential) at the receiver.

ADA4356ABCZ датащи(PDF) 43 Page - Analog Devices

ADA4356ABCZ датащи(HTML) 43 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61

датащи скачать

ссылки URL