ADA4356ABCZ datasheet(36/61 Pages) AD

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Data Sheet

ADA4356

analog.com

Rev. 0

36 of 61

Current Divider Circuit

For the applications with a maximum source current that exceeds the above ranges, additional external circuitry is

required to linearly divide the TIA input current down to fit within the ADA4356’s linear input range.

This current division is not possible with a simple two-resistor current divider to ground, because the TIA input of

the ADA4356 must stay biased at a DC voltage of 1.65V. Thus, a circuit is required that can linearly divide down the

input current while also maintaining the TIA input DC bias voltage. Ideally, this circuit can also be switched into/out

of the main TIA input path in response to dynamic source current levels.

One such circuit is shown in Figure 81. It consists of:

1. C1, capacitor to shunt fast-moving currents to ground.

2. A1, unity-gain voltage buffer to maintain 1.65V at V1, to match the bias voltage at INPUT.

3. S1, switch to connect/disconnect this circuit from the main TIA input path,

R1 and R2, resistor divider network between the photodiode output and the TIA input of the ADA4356.

Figure 81. External High-Speed Current Divider Circuit

When switch S1 is open, all the photodiode’s source current (IPD) enters the TIA at ball INPUT (E1).

When switch S1 is closed, IPD splits into two portions, I1 and I2, according to the ratio of R1 and R2.

Assuming an ideal switch S1, ideal voltage buffer A1, and that TIAREF and INPUT are at the same potential (1.65V), the

portion of IPD current going into the INPUT of the ADA4356 (I2) is given by the following equation:

I2 =

R1 + R2

IPD

The other portion of the divided-down input current (I1) is shunted away via the divider path shown in Figure 81.

AC Ground V1

In high-speed applications, the input photodiode current pulse IPD may be too fast for any active device to absorb

current I1. To shunt large currents quickly, a large capacitor C1 is connected from node V1 to ground to create an AC

ground with a DC bias of 1.65V.

After C1 absorbs the I1 portion of IPD, the DC bias at V1 is perturbed, as shown in the LTspice simulation curves in

Figure 82. Buffer A1 corrects the perturbation by rapidly bringing node V1 back to 1.65V to keep INPUT and TIAREF at

the same DC voltage.

The more zoomed-out simulated transient curves in Figure 83 show multiple input current pulses on IPD, and the

resulting settling behavior of the AC ground at node V1 as A1 brings it back to 1.65V exactly.

INPUT

TIAREF

TIA

OUTPUT

4.7kΩ

2kΩ

1.65V

REF

IPD

CURRENT DIVIDER

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