ADA4356ABCZ datasheet(44/61 Pages) AD

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Data Sheet

ADA4356

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Rev. 0

44 of 61

The ADA4356 differential outputs also support a low power, reduced signal range option (similar to the IEEE 1596.3

standard) via SPI programming. When operating in reduced range mode, the LVDS output driver current reduces to

2mA. This reduction results in a 200mV swing (or 400mV p-p differential) across a 100Ω termination at the receiver.

The LVDS outputs facilitate interfacing with LVDS receivers in custom applications specific ICs (ASICs) and FPGAs for

improved switching performance in noisy environments. To reduce the environmental noise impact, the PCB trace

design recommends single point-to-point net topologies with a 100Ω termination resistor placed as close as possible

to the receiver. Timing errors may result if there is no far end receiver termination, or if there is poor differential trace

routing. To avoid such timing errors, minimize trace lengths and keep the differential output traces close together

and at equal lengths.

Figure 91 shows an example of the FCO and data stream with proper trace length and position. In Figure 91 and Figure

92, D0 is the differential signal, D0AP – D0AN, and D1 is the differential signal, D1AP – D1AN.

Figure 91. Output Timing Example in ANSI-644 Mode (Default)

Figure 92 shows the LVDS output timing example in reduced range mode.

Figure 92. LVDS Output Timing Example in Reduced Range Mode

Figure 93 shows an example of the LVDS output data eye using the ANSI-644 standard (default) with trace lengths of

less than 24inches on standard FR-4 material.

D0Ax 500mV/DIV

D1Ax 500mV/DIV

DCOx 500mV/DIV

FCOx 500mV/DIV

4ns/DIV

D0Ax 400mV/DIV

D1Ax 400mV/DIV

DCOx 400mV/DIV

FCOx 400mV/DIV

4ns/DIV

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