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ADA4356ABCZ датащи(PDF) 46 Page - Analog Devices

номер детали ADA4356ABCZ
подробное описание детали  Programmable Transimpedance, Current to Bits Receiver μModule
PDF  61 Pages
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производитель  AD [Analog Devices]
домашняя страница  http://www.analog.com
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ADA4356ABCZ датащи(HTML) 46 Page - Analog Devices

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Data Sheet
ADA4356
analog.com
Rev. 0
46 of 61
Figure 95. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths Greater than 24inches (Approximate 36inch Trace
Length Result Shown) on Standard FR-4 Material, External 100Ω Far End Termination Only
Figure 96 shows a TIE jitter histogram with trace lengths greater than 24inches on standard FR-4 material.
Figure 96. TIE Jitter Histogram for Trace Lengths Greater than 24inches (Approximate 36inch Trace Length Result Shown) on
Standard FR-4 Material
Two output clocks assist in capturing data from the ADA4356. The DCO clocks the output data and is equal to 4× the
sample clock (CLK) rate for the default mode of operation. Data is clocked out of the ADA4356 and must be captured
on the rising and falling edges of the DCO that supports DDR capturing. The FCO signals the start of a new output
byte and is equal to the sample clock rate in 1× frame mode. For more details, see Figure 6.
When the SPI is used, the DCO phase can be adjusted in approximately 60° increments relative to one data cycle (30°
relative to one DCO cycle). This adjustment allows the user to refine system time margins, if required. The example
DCOP and DCON timing, as shown in Figure 6, is 180° relative to one data cycle (90° relative to one DCO cycle).
In power-on default mode, as shown in Figure 6, the MSB is first in the data output serial stream. This configuration
can be inverted by programming the SPI so that the LSB is first in the data output serial stream.
Digital Output Coding
There are 12 digital output test pattern options available that can be initiated through the SPI. This feature is useful
when validating receiver capture and timing. For the output bit sequencing options available, see Table 15. Some
test patterns have two serial sequential words and can be alternated in various ways depending on the test pattern
chosen.
500
400
300
200
100
–500
–400
–300
–200
–100
0
–0.8
–0.4
0
TIME (ns)
0.4
0.8
EYE: ALL BITS
ULS: 8000/414024
10k
12k
2k
4k
6k
8k
0
–800
–600
–400
–200
0
200
400
600
TIME (ps)



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